Memory element and method of operation thereof

A memory comprising:

• a stored charge element having first and second terminals;
• a first memory access node coupled to the first terminal of the first stored charge element;
• a charge input path having a second memory access node, the charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur;
• a charge output path having a third memory access node, the charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur;
• and
• an amplifying valve having a control terminal coupled to the second terminal of the first stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a memory read node;
• wherein at least one of the first, second and third memory access nodes is a bit node.

A memory comprising:

• a first stored charge element having first and second terminals;
• a first memory access node coupled to the first terminal of the first stored charge element;
• a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur;
• and
• a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur;
• wherein the first stored charge element, the first charge input path, and the first charge output path form in combination a first dynamic memory cell, the memory further comprising a word select line, first, second and third column bit lines, and a second dynamic memory cell having:
• a second stored charge element having first and second terminals;
• a fourth memory access node coupled to the first terminal of the second stored charge element;
• a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur;
• and
• a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur;
• wherein the first and fourth memory access nodes are coupled to the word select line, the second and sixth memory access nodes are coupled to the second column bit line, the third memory access node is coupled to the first column bit line, and the fifth memory access node is coupled to the third column bit line.

A memory comprising:

• a stored charge element having first and second terminals;
• a first memory access node coupled to the first terminal of the first stored charge element;
• a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur;
• a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur;
• and
• a latch having an input/output terminal coupled to the second terminal of the stored charge element;
• wherein at least one of the first, second and third memory access nodes is a bit node, and the charge input path and the charge output path are opposite directions through a bi-directional voltage dropping element having a first terminal coupled to the second terminal of the stored charge device and a second terminal that includes the second and third memory access nodes.

A memory comprising:

• a first stored charge element having first and second terminals;
• a first memory access node coupled to the first terminal of the first stored charge element;
• a first charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur;
• a first charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur;
• a second stored charge element having first and second terminals;
• a fourth memory access node coupled to the first terminal of the second stored charge element;
• a second charge input path having a fifth memory access node, the second charge input path being a charge path into the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the fifth memory access node to the second terminal of the second stored charge element above which conduction occurs and below which significant conduction does not occur;
• and
• a second charge output path having a sixth memory access node, the second charge output path being a charge path from the second terminal of the second stored charge element and having a substantially definite voltage drop threshold from the second terminal of the second stored charge element to the sixth memory access node above which conduction occurs and below which significant conduction does not occur;
• a first inverter having a true input, a complement input, and an output;
• and
• a second inverter having a true input, a complement input, and an output, the output of the first inverter being coupled to the true and complement inputs of the second inverter, and the output of the second inverter being coupled to the true and complement inputs of the first inverter;
• wherein:
• the output of the first inverter is further coupled to the second terminal of the first stored charge element, and the output of the second inverter is further coupled to the second terminal of the second stored charge element;
• at least one of the first, second and third memory access nodes is a bit node;
• at least one of the fourth, fifth and sixth memory access nodes is a bit node;
• the first charge input path and the first charge output path are opposite directions through a first bi-directional voltage dropping element having a first terminal coupled to the second terminal of the first stored charge device and a second terminal that includes the second and third memory access nodes;
• and
• the second charge input path and the second charge output path are opposite directions through a second bi-directional voltage dropping element having a first terminal coupled to the second terminal of the second stored charge device and a second terminal that includes the fifth and sixth memory access nodes.

A memory comprising:

• a stored charge element having first and second terminals;
• a first memory access node coupled to the first terminal of the first stored charge element;
• a charge input path having a second memory access node, the first charge input path being a charge path into the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second memory access node to the second terminal of the first stored charge element above which conduction occurs and below which significant conduction does not occur;
• a charge output path having a third memory access node, the first charge output path being a charge path from the second terminal of the first stored charge element and having a substantially definite voltage drop threshold from the second terminal of the first stored charge element to the third memory access node above which conduction occurs and below which significant conduction does not occur;
• and
• an amplifying valve having a control terminal coupled to the second terminal of the stored charge element, a first current terminal coupled to the first access node, and a second current terminal coupled to a stage output node;
• wherein the second memory access node is coupled to a precharge line and the third memory access node is coupled to a stage input node.

A method of controlling voltage across a stored charge element included in a memory so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage, the respective voltage drop thresholds of the first and second current paths being unequal;
• and
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• attempting to flow current during a third interval through the first current path to increase voltage across the stored charge element to the first voltage;
• and
• sensing current flow during the third interval, a sensed first value of current flow indicating a particular one of the plurality of logical states and a sensed second value of current flow indicating another particular one of the plurality of logical states.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• and
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• wherein:
• the second interval current flowing step is subsequent to the first interval current flowing step;
• the second voltage is indicative of a first logical state;
• and
• the current blocking step comprises blocking current during an interval following and contiguous with the second interval;
• further comprising:
• flowing current during a third interval through the first current path to increase voltage across the stored charge element to a third voltage greater than the second voltage;
• flowing current during a fourth interval subsequent to the third interval through the second current path to decrease voltage across the stored charge element to a fourth voltage greater than the second voltage, the fourth voltage being indicative of a second logical state different than the first logical state;
• and
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with the fourth interval.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• and
• applying the voltage across the stored charge element to a control terminal of an amplifying valve, wherein the amplifying valve has a first conductance characteristic when the voltage across the stored charge element indicates a particular one of the plurality of logical states and has a second conductance characteristic different from the first conductance characteristic when the voltage across the stored charge element indicates another particular one of the plurality of logical states.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• applying the voltage across the stored charge element to an input/output terminal of a latch to establish a logical state thereof;
• and
• detecting the logical state of the latch through one of the first and second current paths.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• and
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• wherein the stored charge element is capacitance of an input/output terminal of a latch, further comprising:
• establishing a logical state of the latch through at least one of the first and second current paths;
• and
• detecting the logical state of the latch through at least one of the first and second current paths.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• and
• applying the voltage across the stored charge element to a control terminal of an amplifying valve, wherein:
• the first interval current flowing step comprises establishing a first voltage differential across a series combination of the first current path and the stored charge element, the first voltage differential being greater than the first substantially definite voltage drop threshold by an amount sufficient to establish a precharge voltage across the stored charge element, wherein the amplifying valve has a first conductance characteristic;
• and
• the second interval current flowing step comprises establishing a second voltage differential across a series combination of the second current path and the stored charge element, the second voltage differential being greater than the second substantially definite voltage drop threshold by an amount sufficient to established a first predetermined voltage across the stored charge element different than the precharge voltage, wherein the amplifying valve has a second conductance characteristic to indicate a first logical state;
• and
• determining a conductance characteristic of the amplifying valve to indicate an output logical state, the output logical state being the first logical state when the conductance characteristic of the amplifying valve is the second conductance characteristic.

A method of controlling voltage across a stored charge element so as to indicate a particular one of a plurality of different logical states, comprising:

• flowing current during a first interval through a first current path having a first substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to increase voltage across the stored charge element to a first voltage;
• flowing current during a second interval through a second current path having a second substantially definite voltage drop threshold above which conduction occurs with no significant deterioration over time and below which significant conduction does not occur, to decrease voltage across the stored charge element to a second voltage, the second voltage being less than the first voltage;
• blocking current through the first and second current paths by use of the first and second substantially definite voltage drop thresholds during an interval following and contiguous with at least one of the first and second intervals;
• linking N two-terminal memory cells in a closed loop chain of N memory cells, the memory cells storing one of a high value of voltage V.sub.H to indicate a first logical state and a low value of voltage V.sub.L to indicate a second logical state different than the first logical state;
• performing the first interval flowing step wherein the substantially definite voltage drop thresholds of the charge input paths of the N memory cells are substantially equal to a value V.sub.I ;
• and
• performing the second interval flowing step wherein the substantially definite voltage drop thresholds of the charge output paths of the N memory cells are substantially equal to a value V.sub.O ;
• wherein V.sub.I and V.sub.O are related to V.sub.H and V.sub.L by the expression V.sub.H -V.sub.L .ltoreq.(V.sub.I +V.sub.O)(N-2)/N.