Memory cell and method of operation thereof

A dynamic memory comprising:

• a plurality of memory cells arranged in an array and coupled to a plurality of word select lines and column bit lines, each memory cell having characteristics of a stored charge device that stores a voltage indicative of either a first or second logical state in series with a voltage dropping device that has asymmetrical substantially definite voltage drop characteristics V.sub.s and V.sub.w while conducting in each direction;
• means for idling the memory by placing idle voltages on the word select lines and the column bit lines so that voltages across elements of the memory cells having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• means for placing a voltage on a first one of the word select lines to access one of the memory cells coupled thereto, the voltage on the first word select line being of a value so that V.sub.s is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing a first logical state to perturb the idle voltage on a first one of the column bit lines coupled to the accessed cell while voltages across elements of any others of the cells coupled to the first column bit line having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w, and V.sub.s is not exceeded across the element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing a second logical state to avoid perturbing the idle voltage on the first column bit line;
• and
• means for sensing any perturbation in the first column bit line to determine the logical state of the accessed cell.

A dynamic memory comprising:

• a plurality of memory cells arranged in an array and coupled to a plurality of word select lines and column bit lines, each memory cell having characteristics of a stored charge device that stores a voltage indicative of either a first or second logical state in series with a voltage dropping device that has asymmetrical substantially definite voltage drop characteristics V.sub.s and V.sub.w while conducting in each direction;
• means for idling the memory by placing idle voltages on the word select lines and the column bit lines so that voltages across elements of the memory cells having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• means for placing a voltage on a first one of the word select lines to access one of the memory cells coupled thereto;
• and
• means for placing a voltage indicative of either the first or second logical state on a first one of the column bit lines coupled to the selected cell while voltages across elements of any others of the cells coupled to the first column bit line having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• wherein the voltage on the first word select line is of a value so that V.sub.s is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing the first logical state and the voltage on the first column bit line is indicative of the second logical state, and V.sub.w is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing the second logical state and the voltage on the first column bit line is indicative of the first logical state, and otherwise neither V.sub.s nor V.sub.w is exceeded across elements of any others of the cells coupled to the first column bit line having the voltage dropping device characteristics.

A dynamic memory comprising:

• a plurality of row select lines;
• a plurality of column bit lines;
• a plurality of memory cells;
• wherein:
• each memory cell is associated with one of the word select lines and one of the column bit lines so that at least two of the memory cells share a common word select line and at least two of the memory cells share a common column bit line;
• and
• each memory cell comprising a stored charge device and a voltage dropping device, the stored charge device and the voltage dropping device being serially coupled between the associated word select line and the associated column bit line, the stored charge device having a charge state indicative of either a first logical state or a second logical state, and the voltage dropping device being a bi-directional device having a substantially definite first voltage drop while conducting in one direction and a substantially definite second voltage drop while conducting in another direction, the first and second voltage drops being unequal;
• means for initializing the word select lines to an idle voltage;
• means for initializing a first subset of the column bit lines to a first precharge voltage, the relationship between the idle voltage and the first precharge voltage being such that voltages across the voltage dropping devices do not exceed the first and second voltage drops regardless of the charge state of the stored charge devices;
• means for initializing a second subset of the column bit lines to a second precharge voltage, the relationship between the idle voltage and the second precharge voltage being such that voltages across the voltage dropping devices do not exceed the first and second voltage drops regardless of the charge state of the stored charge devices;
• means for driving the common word select line to a read voltage to access the memory cells coupled to the common word select line, the read voltage having a value that in combination with the first precharge voltage and the charge state:
• causes voltages across the voltage dropping devices of the memory cells coupled to the common word select line not to exceed the first or second voltage drops when the charge state is indicative of the first logical state, whereby the column bit lines coupled to the accessed memory cells having the first logical state are not perturbed;
• and
• causes voltage across the voltage dropping device of the memory cells coupled to the common word select line to exceed the second voltage drop when the charge state is indicative of the second logical state, whereby the column bit lines coupled to the accessed memory cells having the second logical state are perturbed and acquire a modified voltage, and the charge state of the accessed memory cells having the second logical state become indicative of the first logical state;
• and the read voltage further having a value that in combination with the second precharge voltage and the charge state, voltages across the voltage dropping devices do not exceed the first or second voltage drops regardless of the charge state of the stored charge devices;
• and
• means for sensing the logical modes of the accessed memory cells based on whether the column bit lines are perturbed;
• wherein the relationship between the idle voltage and the modified voltage is such that voltages across the voltage dropping devices do not exceed the first or second voltage drops regardless of the charge state of the stored charge devices.

A dynamic memory comprising:

• a plurality of row select lines;
• a plurality of column bit lines;
• a plurality of memory cells;
• wherein:
• each memory cell is associated with one of the word select lines and one of the column bit lines so that at least two of the memory cells share a common word select line and at least two of the memory cells share a common column bit line;
• and
• each memory cell comprising a stored charge device and a voltage dropping device, the stored charge device and the voltage dropping device being serially coupled between the associated word select line and the associated column bit line, the stored charge device having a charge state indicative of either a first logical state or a second logical state, and the voltage dropping device being a bi-directional device having a substantially definite first voltage drop while conducting in one direction and a substantially definite second voltage drop while conducting in another direction, the first and second voltage drops being unequal;
• means for driving the common word select line to a write voltage to write the accessed memory cells;
• means for driving a first subset of the column bit lines to a logical mode -dependent voltage based on logical values of data to be written to the accessed memory cells;
• and
• means for driving a second subset of the column bit lines to a non-select voltage, the relationship between the write voltage and the non-select voltage being such that voltages across the voltage dropping devices do not exceed the first or second voltage drops regardless of the charge state of the stored charge devices;
• the relationship between the charge state, the write voltage, and the logical mode -dependent voltage being such that:
• when the charge state and the logical mode -dependent voltage are indicative of the first logical state, voltages across the voltage dropping devices do not exceed the first or second voltage drops;
• and
• when the charge state is indicative of the first logical state and the logical mode -dependent voltage is indicative of the second logical state, voltages across the voltage dropping devices exceed the first voltage drop.

A method to read a dynamic memory comprising a plurality of memory cells arranged in an array and coupled to a plurality of word select lines and column bit lines, each memory cell having characteristics of a stored charge device that stores a voltage indicative of either a first or second logical state in series with a voltage dropping device that has asymmetrical substantially definite voltage drop characteristics V.sub.s and V.sub.w while conducting in each direction, the method comprising:

• idling the memory by placing idle voltages on the word select lines and the column bit lines so that voltages across elements of the memory cells having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• placing a voltage on a first one of the word select lines to access one of the memory cells coupled thereto, the voltage on the first word select line being of a value so that V.sub.s is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing a first logical state to perturb the idle voltage on a first one of the column bit lines coupled to the accessed cell while voltages across elements of any others of the cells coupled to the first column bit line having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w, and V.sub.s is not exceeded across the element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing a second logical state to avoid perturbing the idle voltage on the first column bit line;
• and
• sensing any perturbation in the first column bit line to determine the logical state of the accessed cell.

A method to write a dynamic memory comprising a plurality of memory cells arranged in an array and coupled to a plurality of word select lines and column bit lines, each memory cell having characteristics of a stored charge device that stores a voltage indicative of either a first or second logical state in series with a voltage dropping device that has asymmetrical substantially definite voltage drops V.sub.s and V.sub.w while conducting in each direction, the method comprising:

• idling the memory by placing idle voltages on the word select lines and the column bit lines so that voltages across elements of the memory cells having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• placing a voltage on a first one of the word select lines to access at least one of the memory cells coupled thereto;
• and
• placing a voltage indicative of either the first or second logical state on a first one of the column bit lines coupled to the selected cell while voltages across elements of any of the cells other than the accessed cell coupled to the first column bit line having the voltage dropping device characteristics do not exceed V.sub.s or V.sub.w ;
• wherein the voltage on the first word select line is of a value so that V.sub.s is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing the first logical state and the voltage on the first column bit line is indicative of the second logical state, and V.sub.w is exceeded across an element of the accessed cell having the voltage dropping device characteristics when the accessed cell is storing the second logical state and the voltage on the first column bit line is indicative of the first logical state.

A method to read a dynamic memory cell that comprises a cell select node, a bit node, a stored charge device, and a voltage dropping device, wherein the stored charge device and the voltage dropping device are serially coupled between the cell select node and the bit node, the stored charge device has either a first charge state indicative of a first logical state or a second charge state indicative of a second logical state, and the voltage dropping device has a substantially definite first voltage drop while conducting in a direction from the bit node to the cell select node, and a substantially definite second voltage drop while conducting in a direction from the cell select node to the bit node, the first and second voltage drops being unequal, the method comprising:

• initializing the cell select node to an idle voltage;
• initializing the bit node to a precharge voltage, the relationship between the idle voltage and the precharge voltage being such that voltage across the voltage dropping device does not exceed the first and second voltage drops;
• driving the cell select node to a read voltage, the relationship between the read voltage and the precharge voltage being such that voltage across the voltage dropping device does not exceed the first and second voltage drops when the stored charge device has the first charge state, and voltage across the voltage dropping device exceeds the first voltage drop when the stored charge device has the second charge state to share charge between the stored charge device and the bit node, thereby perturbing the bit node and causing the stored charge device to have a modified charge state;
• sensing the logical mode based on the perturbation of the bit node;
• driving the bit node to a logical mode -dependent voltage based on the sensed logical mode;
• and
• driving the cell select node to a write voltage, the relationship between the write voltage and the logical mode -dependent voltage being such that when the stored charge device has the first charge state and the logical mode -dependent voltage reflects the first logical state, voltage across the voltage dropping device does not exceed the first and second voltage drops, while when the stored charge device has the modified charge state and the logical mode -dependent voltage reflects the second logical state, voltage across the voltage dropping device exceeds the second voltage drop to return the stored charge device to substantially the second charge state.

A method to write a data bit to a dynamic memory cell that comprises a cell select node, a bit node, a stored charge device, and a voltage dropping device, wherein the stored charge device and the voltage dropping device are serially coupled between the cell select node and the bit node, the stored charge device has either a first charge state indicative of a first logical state or a second charge state indicative of a second logical state or an intermediate charge state indicative of an indeterminate logical state, and the voltage dropping device has a substantially definite first voltage drop while conducting in a direction from the bit node to the cell select node, and a substantially definite second voltage drop while conducting in a direction from the cell select node to the bit node, the first and second voltage drops being unequal, the method comprising:

• driving the bit node to a logical mode -dependent voltage based on the data bit;
• and
• driving the cell select node to a write voltage, the relationship between the write voltage and the logical mode -dependent voltage being such that when the stored charge device has the first charge state and the logical mode -dependent voltage reflects the first logical state, voltage across the voltage dropping device does not exceed the first and second voltage drops, while when the stored charge device has either the first charge state or the intermediate charge state and the logical mode -dependent voltage reflects the second logical state, voltage across the voltage dropping device exceeds the second voltage drop to set the stored charge device to the second charge state.

A method to access a dynamic memory comprising:

• a plurality of row select lines;
• a plurality of column bit lines;
• and
• a plurality of memory cells;
• wherein each memory cell is associated with one of the word select lines and one of the column bit lines so that at least two of the memory cells share a common word select line and at least two of the memory cells share a common column bit line;
• and
• wherein each memory cell comprising a stored charge device and a voltage dropping device, the stored charge device and the voltage dropping device being serially coupled between the associated word select line and the associated column bit line, the stored charge device having a charge state indicative of either a first logical state or a second logical state, and the voltage dropping device being a bi-directional device having a substantially definite first voltage drop while conducting in one direction and a substantially definite second voltage drop while conducting in another direction, the first and second voltage drops being unequal;
• the method comprising:
• initializing the word select lines to an idle voltage;
• initializing a first subset of the column bit lines to a first precharge voltage, the relationship between the idle voltage and the first precharge voltage being such that voltages across the voltage dropping devices do not exceed the first and second voltage drops regardless of the charge state of the stored charge devices;
• initializing a second subset of the column bit lines to a second precharge voltage, the relationship between the idle voltage and the second precharge voltage being such that voltages across the voltage dropping devices do not exceed the first or second voltage drops regardless of the charge state of the stored charge devices;
• driving the common word select line to a read voltage to access the memory cells coupled to the common word select line, the read voltage having a value that in combination with the first precharge voltage and the charge state:
• causes voltages across the voltage dropping devices of the memory cells coupled to the common word select line not to exceed the first or second voltage drops when the charge state is indicative of the first logical state, whereby the column bit lines coupled to the accessed memory cells having the first logical state are not perturbed;
• and
• causes voltages across the voltage dropping devices of the memory cells coupled to the common word select line to exceed the second voltage drop when the charge state is indicative of the second logical state, whereby the column bit lines coupled to the accessed memory cells having the second logical state are perturbed and acquire a modified voltage, and the charge state of the accessed memory cells having the second logical state become indicative of the first logical state;
• and the read voltage further having a value that in combination with the second precharge voltage and the charge state, voltages across the voltage dropping devices do not exceed the first and second voltage drops regardless of the charge state of the stored charge devices;
• and
• sensing the logical modes of the accessed memory cells based on whether the column bit lines are perturbed;
• wherein the relationship between the idle voltage and the modified voltage is such that voltages across the voltage dropping devices do not exceed the first or second voltage drops regardless of the charge state of the stored charge devices.

A method to write a dynamic memory comprising:

• a plurality of row select lines;
• a plurality of column bit lines;
• and
• a plurality of memory cells;
• wherein each memory cell is associated with one of the word select lines and one of the column bit lines so that at least two of the memory cells share a common word select line and at least two of the memory cells share a common column bit line;
• and
• wherein each memory cell comprising a stored charge device and a voltage dropping device, the stored charge device and the voltage dropping device being serially coupled between the associated word select line and the associated column bit line, the stored charge device having a charge state indicative of either a first logical state or a second logical state, and the voltage dropping device being a bi-directional device having a substantially definite first voltage drop while conducting in one direction and a substantially definite second voltage drop while conducting in another direction, the first and second voltage drops being unequal;
• the method comprising:
• driving the common word select line to a write voltage to write the accessed memory cells;
• driving a first subset of the column bit lines to a logical mode -dependent voltage based on logical values of data to be written to the accessed memory cells;
• and
• driving a second subset of the column bit lines to a non-select voltage, the relationship between the write voltage and the non-select voltage being such that that voltages across the voltage dropping devices do not exceed the first and second voltage drops regardless of the charge state of the stored charge devices;
• the relationship between the charge state, the write voltage, and the logical mode -dependent voltage being such that:
• when the charge state and the logical mode -dependent voltage are indicative of the first logical state, voltages across the voltage dropping devices do not exceed the first or second voltage drops;
• and
• when the charge state is indicative of the first logical state and the logical mode -dependent voltage is indicative of the second logical state, voltages across the voltage dropping devices exceed the first voltage drop.

A memory cell comprising:

• a first memory cell node;
• a second memory cell node;
• a third memory cell node;
• a stored charge device coupled between the first and second cell nodes;
• a first voltage dropping device having a definite voltage drop while conducting in one direction and no ability to conduct in the opposite direction, the first voltage dropping device being coupled between the third cell node and the second cell node so that it conducts in the direction from the third to the second cell node;
• and
• a second voltage dropping device having a definite voltage drop while conducting in one direction and no ability to conduct in the opposite direction, the second voltage dropping device being coupled between the second cell node and the third cell node so that it conducts in the direction from the second to the third cell node;
• wherein the voltage drops of the first and second voltage dropping devices are unequal.