Semiconductor memory device having improved bit line distribution

A semiconductor memory comprising:

• a memory cell array including 2N (N.gtoreq.2) bit line pairs arranged in columns, each of the bit line pairs coupled to a plurality of memory cells;
• a first sense amplifier array having N first sense amplifier circuits arranged in a first column at one side of the memory cell array, each of the first sense amplifier circuits coupled to one of the bit line pairs, thereby coupling the first sense amplifier array to N of the bit line pairs;
• and
• a second sense amplifier array having N second sense amplifier circuits arranged in a second column at the opposite side of the memory cell array, each of the second sense amplifier circuits coupled to another of the bit line pairs, thereby coupling the second sense amplifier array to the other N of the bit line pairs,
• wherein a first group of M (M.gtoreq.2) adjacent bit line pairs is distributed to one of the sense amplifier arrays and a second group of M adjacent bit line pairs bordering the first group is distributed to the other sense amplifier array, and
• each of the bit line pairs is jogged at the end near its corresponding sense amplifier circuit to create regions for shunting a first signal line and a second signal line, and to allow the sense amplifier circuits to be arranged at regular intervals.

A semiconductor memory comprising:

• first, second, third and fourth adjacent bit line pairs arranged in this order in parallel;
• a first sense amplifier circuit connected to the right end of the first bit line pair;
• a second sense amplifier circuit connected to the left end of the second bit line pair;
• a third sense amplifier circuit connected to the left end of the third bit line pair;
• and
• a fourth sense amplifier circuit connected to the right end of the fourth bit line pair,
• wherein the first sense amplifier is adjacent to the fourth sense amplifier, and the second sense amplifier is adjacent to the third sense amplifier.

A semiconductor memory comprising:

• first, second, third and fourth bit line pairs arranged in this order in parallel;
• a first sense amplifier circuit connected to the right end of the first bit line pair;
• a second sense amplifier circuit connected to the left end of the second bit line pair;
• a third sense amplifier circuit connected to the left end of the third bit line pair;
• a fourth sense amplifier circuit connected to the right end of the fourth bit line pair;
• and
• a shunt region for shunting wirings in different layers, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits.

A semiconductor memory comprising:

• first, second, third and fourth bit line pairs arranged in this order in parallel;
• a first sense amplifier circuit connected to the right end of the first bit line pair;
• a second sense amplifier circuit connected to the left end of the second bit line pair;
• a third sense amplifier circuit connected to the left end of the third bit line pair;
• a fourth sense amplifier circuit connected to the right end of the fourth bit line pair;
• a first equalizing signal line for providing a control signal for the MOS transistors, the first equalizing signal line being integral with gate electrodes of the MOS transistors;
• a second equalizing signal line for bypassing the control signal;
• and
• a shunt region for shunting the first equalizing signal line and the second equalizing signal line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits,
• wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

A semiconductor memory comprising:

• first, second, third and fourth bit line pairs arranged in this order in parallel;
• a first sense amplifier circuit connected to the right end of the first bit line pair;
• a second sense amplifier circuit connected to the left end of the second bit line pair;
• a third sense amplifier circuit connected to the left end of the third bit line pair;
• a fourth sense amplifier circuit connected to the right end of the fourth bit line pair;
• a first intermediate voltage line for providing the intermediate voltage for source/drain electrodes of the MOS transistors;
• a second intermediate voltage line for bypassing the intermediate voltage;
• and
• a shunt region for shunting the first intermediate voltage line and the second intermediate voltage line, the shunt region being bounded by the right ends of the second and the third bit line pairs and the first and the fourth sense amplifier circuits,
• wherein each of the sense amplifier circuits includes an equalizing circuit, each of the equalizing circuits having MOS transistors for equalizing its corresponding bit line pair with an intermediate voltage.

A semiconductor memory comprising:

• first, second, third, fourth, fifth, and sixth bit line pairs arranged in this order in parallel;
• a first sense amplifier circuit connected to the right end of the first bit line pair;
• a second sense amplifier circuit connected to the left end of the second bit line pair;
• a third sense amplifier circuit connected to the left end of the third bit line pair;
• a fourth sense amplifier circuit connected to the left end of the fourth bit line pair;
• a fifth sense amplifier circuit connected to the left end of the fifth bit line pair;
• and
• a sixth sense amplifier circuit connected to the right end of the sixth bit line pair.