Low power adder for accumulation

A low-power method for accumulating for use in an integrated circuit performing an accumulate operation on R, K-bit, two's complement binary input numbers, R being an integer .ltoreq.2.sup.L, where L is a predetermined integer value, said accumulate operation producing a N-bit, two's complement sum, wherein the most significant bit (MSB) of said K-bit input numbers is a sign bit and N is a second predetermined integer value no smaller than K+L, said method comprising the steps of:

• receiving said input numbers one by one;
• adding a K-bit binary offset equaling 2.sup.K-1 to each of said input numbers to generate corresponding K-bit, positive input numbers;
• accumulating said positive input numbers one by one into an N-bit, positive sum;
• and
• subtracting an N-bit, two's complement offset equaling R*2.sup.K-1 from said N-bit positive sum to produce said N-bit, two's complement sum;
• said N-bit two's complement sum being identical to the sum of said R, K-bit, two's complement input numbers,
• the adding step minimizing the transition probability of higher order bits of the positive sum as said positive sum is accumulated, causing said integrated circuit to use less power to accumulate said 2's complement input numbers than when said integrated circuit directly accumulates said 2's complement input numbers without said adding step.

For use in an integrated circuit, a low-power circuit for accumulating R, K-bit, two's complement binary input numbers, R being an integer .ltoreq.2.sup.L, where L is a predetermined integer value, said accumulating producing a N-bit, two's complement sum of said K-bit, two's complement numerical inputs, wherein the most significant bit (MSB) of said numerical inputs is a sign bit and N is a second predetermined integer value no smaller than K+L, said circuit comprising:

• An input converter that receives said two's complement inputs one by one and adds a K-bit binary offset equaling 2.sup.K-1 to each of said input numbers to generate corresponding K-bit, positive numerical inputs;
• A two's complement adder with a first input coupled to said input converter's output and a second input coupled to a negative offset line providing a two's complement, N-bit negative offset value equaling -R*2.sup.K-1 ;
• said adder accumulating said positive inputs one by one into a N-bit, positive sum and then, following accumulation of said R positive inputs, adding said N-bit, negative offset value to said positive sum to produce said N-bit two's complement sum;
• said N-bit two's complement sum being identical to the sum of said R, K-bit, two's complement input numbers,
• such that the input converter's addition of the K-bit binary offset minimizes the transition probability of higher order bits of said positive sum accumulated by said adder, causing said integrated circuit to use less power when accumulating said 2's complement input numbers than integrated circuits that directly accumulate said 2's complement input numbers without the input conversion.