Self-timing power-up circuit

Abstract

An improved power-up circuit formed in an integrated circuit for generating a power-up pulse for integrated circuit devices. The present invention includes an input stage, an output stage, and a pulse control circuit. The input stage receives a supply voltage rising from a reference ground to a steady supply voltage upon power-up. The input stage generates a logic low state for a selected period of time, and a logic high state thereafter. An output stage is connected to the input stage, and generates a logic high state when the input stage is generating the logic low state. The output stage switches to the logic low state when the input stage switches to the logic high state after the selected time period. The logic high and low states sequentially generated by the output stage define the power-up pulse. The pulse control circuit is connected between the input and output of the output stage for controlling the width of the power-up pulse. When the output of the output stage switches to the logic high state, the pulse control circuit prevents the output stage from switching to the logic low state for a selected delay period to ensure a minimum width for the generated power-up pulse. Hence, the power-up circuit consistently produces a proper power-up pulse regardless of the ramp-up rate of the supply voltage and power glitches associated with the supply voltage.

Dependencies are inferred from the claim text.