Phase error control for color wheel

A method of providing a color wheel sync signal for synchronizing a color wheel to an incoming video signal, where said video signal has been sampled with a pixel clock and consists of a series of frames separated in accordance with a vertical sync signal, and where said color wheel generates at least one index signal per revolution, comprising the steps of:

• receiving an input signal that causes a potential phase difference between said vertical sync signal and one of said index signal and said color wheel sync signal;
• comparing said one of said index signal and said color wheel sync signal to said vertical sync signal, thereby providing a phase error value;
• dividing said pixel clock by one-half the number of pixels per line, thereby providing a divided pixel clock signal;
• adding said phase error value to the number of lines in one frames;
• and
• dividing said divided pixel clock signal by the result of said adding step, thereby providing said color wheel sync signal.

A method of providing a color wheel sync signal for synchronizing a color wheel to an incoming video signal, where said video signal has been sampled with a pixel clock and consists of a series of frames separated in accordance with a vertical sync signal, and where said color wheel generates at least one index signal per revolution, comprising the steps of:

• receiving an input signal that causes a potential phase difference between said vertical sync signal and one of said index signal and said color wheel sync signal;
• comparing said one of index signal and said color wheel sync signal to said vertical sync signal, thereby providing a phase error value;
• dividing said pixel clock by the number of pixels per line, thereby providing_a divided pixel clock signal;
• adding said phase error value to the number of lines in one field;
• and
• dividing said divided pixel clock signal by the result of said adding step, thereby providing said color wheel sync signal.

A phase error control unit for providing a color wheel sync signal for a color wheel in a display system that samples an incoming video signal with a pixel clock and converts the sampled signal from a series of interlaced fields to a series of frames separated in accordance with a vertical sync signal, and where said color wheel generates an index signal once per revolution, comprising:

• an input signal that causes said incoming video signal to be switched such that a potential phase difference occurs between said vertical sync signal and one of said index signal and said color wheel sync signal;
• a phase comparator for comparing one of said index signal and said color wheel sync signal to said vertical sync signal, thereby providing a phase error value;
• an adder for receiving said phase error value from said phase comparator and for adding said phase error value to a value representing twice the number of lines per frame;
• a first divide-by-N divider for dividing said pixel clock by one-fourth the number of pixels per line;
• and
• a second divide-by-N divider for dividing the output of said first divide-by-N counter by the output of said adder, thereby providing said color wheel sync signal.

A phase error control unit for providing a color wheel sync signal for a color wheel in a display system that samples an incoming video signal with a pixel clock to provide a series of frames separated in accordance with a vertical sync signal, and where said color wheel generates an index signal once per revolution, comprising:

• an input signal that causes said incoming video signal to be switched such that a potential phase difference occurs between said vertical sync signal and one of said index signal and said color wheel sync signal;
• a phase comparator for comparing one of said index signal and said color wheel sync signal to said vertical sync signal, thereby providing a phase error value;
• an adder for receiving said phase error value from said phase comparator and for adding said phase error value to a value representing the number of lines per frame;
• a first divide-by-N divider for dividing said pixel clock by one-half the number of pixels per line;
• and
• a second divide-by-N divider for dividing the output of said first divide-by-N counter by the output of said adder, thereby providing said color wheel sync signal.