Digital/analog converter having separately formed voltage dividing resistance regions

A converter comprising:

• a semiconductor substrate of a first conductivity type;
• a plurality of well regions of a second conductivity type, each formed separately on the semiconductor substrate;
• an input resistance region of the first conductivity type formed in one of the well regions;
• ladder resistance regions of the first conductivity type respectively formed in the well regions;
• an output resistance region of the first conductivity type formed in another one of the well regions;
• and
• a plurality of impurity diffusion regions of the second conductivity type formed in the well regions, respectively, separated from the input, ladder, and output resistance regions, respectively, for applying backward bias voltages to the respective input, ladder, and output resistance regions.

An N bit (where N is an integer) converter having separately formed voltage dividing resistance regions comprising:

• a semiconductor substrate of a first conductivity type;
• (N+1) well regions of a second conductivity type, each formed separately on the semiconductor substrate;
• an input resistance region of the first conductivity type formed in one of the (N+1) well regions;
• (N-1) ladder resistance regions of the first conductivity type formed in respective well regions;
• an output resistance region of the first conductivity type formed in another one of the (N+1) well regions;
• and
• (N+1) impurity diffusion regions of the second conductivity type formed in the well regions, respectively, separated from the input, ladder, and output resistance regions, respectively, for applying backward bias voltages to the respective input, ladder, and output resistance regions.