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US 5,691,661 AGranted
Pulse generating circuit and a semiconductor memory device provided with the same
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsTatsuya Fukuda, Shigeru Mori, Masanori Hayashikoshi, Seiji Sawada
Life of this patent
Estimating the term…
Abstract
A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.
Claims9
A pulse signal generating circuit comprising:
- signal generating means for generating a pulse signal at a pulse period;
- temperature detecting means for detecting an operation temperature and producing a detection signal therefrom;
- and
- control means for controlling the pulse period of the pulse signal, which is generated by said signal generating means in response to said detection signal supplied from said temperature detecting means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operation temperature and when the operation temperature varies from the normal operation temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operation temperature;
- said signal generating means includes a plurality of inverters, which are mutually connected in a ring form, and
- said control means includes switch means for selectively forming a ring oscillator formed of said plurality of inverters, or formed of some of said plurality of inverters, in response to said detection signal supplied from said temperature detecting means.
4 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means,
- said pulse signal generating means including
- i) a first control signal generating circuit for outputting a first internal voltage and including
- a reference voltage generator having
- a first node coupled to receive a first supply voltage,
- a current source connected to said first node,
- a second node coupled between said said current source and a second supply voltage, and
- a resistor connected between said second node and said second supply voltage and having a predetermined temperature characteristic, said reference voltage being supplied from said second node at a voltage level dependent on temperature, and
- resistance control means coupled to the second node and said first supply voltage for controlling the first internal voltage depending on operational temperature of said resistor, and
- ii signal generating means to be driven by said first internal voltage outputted from said first control signal generating circuit for generating the pulse signal at a pulse period, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature of said resistor and when the operational temperature of said resistor varies from the normal operation temperature, the internal voltage controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in the operational temperature of said resistor.
10 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and
- refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means;
- said pulse signal generating means including;
- signal generating means for generating a pulse signal,
- temperature detecting means for detecting an operation temperature to supply a detection signal therefrom, and
- control means for controlling a period of a pulse signal, which is to be generated by said signal generating means in response to said detection signal supplied from said temperature detection means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature detected by said temperature detecting means and when the operational temperature detected by said temperature detecting means varies from the normal operational temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operational temperature detected by said temperature detecting means,
- said signal generating means includes a plurality of inverters which are mutually connected in a ring form, and
- said control means includes switch means which is responsive to said detection signal supplied from said temperature detecting means to selectively form a first ring oscillator, which is formed of said plurality of inverters, or a second ring oscillator, which is formed of some of said plurality of inverters.
8 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and
- refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means;
- said pulse signal generating means including;
- signal generating means for generating a pulse signal,
- temperature detecting means for detecting an operation temperature to supply a detection signal therefrom, and
- control means for controlling a period of a pulse signal, which is to be generated by said signal generating means in response to said detection signal supplied from said temperature detection means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature detected by said temperature detecting means and when the operational temperature detected by said temperature detecting means varies from the normal operational temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operational temperature detected by said temperature detecting means,
- said signal generating means includes a plurality of inverters which are mutually connected in a ring form, and
- said control means includes capacitance means and connected means for connecting said capacitance means to a node located between adjacent two of said inverters in response to said detection signal supplied from said temperature detecting means.
8 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and
- refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means;
- said pulse signal generating means including;
- signal generating means for generating a pulse signal,
- temperature detecting means for detecting an operation temperature to supply a detection signal therefrom, and
- control means for controlling a period of a pulse signal, which is to be generated by said signal generating means in response to said detection signal supplied from said temperature detection means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature detected by said temperature detecting means and when the operational temperature detected by said temperature detecting means varies from the normal operational temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operational temperature detected by said temperature detecting means,
- said signal generating means includes a plurality of inverters which are mutually connected in a ring form, and
- said control means includes first capacitance means having a first capacitance value, second capacitance means having a second capacitance value smaller than said first capacitance value, and connecting means, which is responsive to said detection signal supplied from said temperature detecting means to selectively connect said first and second capacitance means to a node located between adjacent tow of said inverters.
8 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and
- refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means;
- said pulse signal generating means including;
- signal generating means for generating a pulse signal,
- temperature detecting means for detecting an operation temperature to supply a detection signal therefrom, and
- control means for controlling a period of a pulse signal, which is to be generated by said signal generating means in response to said detection signal supplied from said temperature detection means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature detected by said temperature detecting means and when the operational temperature detected by said temperature detecting means varies from the normal operational temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operational temperature detected by said temperature detecting means,
- said signal generating means includes a plurality of inverters which are mutually connected in a ring form, and
- said control means includes resistance means, and connecting means which is responsive to said detection signal supplied from said temperature detecting means to connect said resistance means between adjacent two of said inverters.
8 more elements
A semiconductor memory device comprising:
- dynamic memory means for storing data;
- pulse signal generating means for generating a pulse signal;
- and
- refresh control means for controlling a refresh cycle in a self refresh mode of said dynamic memory means in response to said pulse signal generated by said pulse signal generating means;
- said pulse signal generating means including;
- signal generating means for generating a pulse signal,
- temperature detecting means for detecting an operation temperature to supply a detection signal therefrom, and
- control means for controlling a period of a pulse signal, which is to be generated by said signal generating means in response to said detection signal supplied from said temperature detection means, wherein
- the pulse signal generated by said signal generating means has a pulse period P at a normal operational temperature detected by said temperature detecting means and when the operational temperature detected by said temperature detecting means varies from the normal operational temperature, the control means controls the pulse period of the pulse signal to increase or decrease in inverse direction to the variance in operational temperature detected by said temperature detecting means,
- said signal generating means includes a plurality of inverters which are mutually connected in a ring form, and
- said control means includes first resistance means having a first resistance value, second resistance means having a second resistance value smaller than said first resistance value, and connecting means for selectively connecting said first and second resistance means between adjacent two of said inverters in response to said detection signal supplied from said temperature detecting means.
8 more elements
Dependencies are inferred from the claim text.