Clock synchronization scheme for fractional multiplication systems
AssigneeInternational Business Machines Corporation
InventorsRobert Edward Busch, Kenneth Michael Zick, Robert Maurice Houle
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Abstract
A circuit for synchronizing a multiplied system clock signal includes a device for generating a system clock signal, a first device that receives the system clock signal and generates a synchronization signal and at least one second device that receives the system clock signal and the synchronization signal. Each of the second devices includes a device for multiplying the system clock signal to produce the multiplied system clock signal and a device for synchronizing the multiplied system clock signal with each other multiplied system clock signal produced by the other second devices based on the synchronization signal.
Claims10
A circuit for synchronizing a multiplied system clock signal, comprising:
- means for generating a system clock signal;
- a first device, operatively connected to said generating means, for receiving said system clock signal, and for generating a synchronization signal;
- and
- a plurality of second devices, operatively connected to said generating means and said first device, for receiving said system clock signal and said synchronization signal, each of said second devices including a multiplied clock generator circuit for outputting said multiplied system clock signal and for synchronizing said multiplied system clock signal with said system clock signal, such that each said multiplied system clock signal produced by one of said second devices is synchronized and in phase with other multiplied system clock signals produced by other ones of said second devices,
- wherein said multiplied system clock signal comprises a non-integer fractional multiple of said system clock signal,
- wherein said multiplied clock generator circuit comprises:
- first and second logic circuits;
- a phase/frequency detector circuit coupled to each of said first and second logic circuits;
- and
- an oscillator circuit for receiving an output of said phase/frequency detector circuit, said oscillator circuit including means for outputting said multiplied system clock signal.
A circuit for synchronizing a multiplied system clock signal comprising:
- means for generating a system clock signal;
- a first device, operatively connected to said generating means for receiving said system clock signal and for generating a synchronization signal;
- and
- a plurality of second devices, operatively connected to said generating means and said first device, for receiving said system clock signal and said synchronization signal, each of said second devices including a multiplied clock generator circuit for outputting said multiplied system clock signal and for synchronizing said multiplied system clock signal with said system clock signal, such that each said multiplied system clock signal produced by one or said second devices is synchronized and in phase with other multiplied system clock signals produced by other ones of said second devices,
- wherein said multiplied system clock signal comprises a non-integer fractional multiple of said system clock signal,
- wherein said first device comprises a second multiplied clock generator circuit including:
- third and fourth logic circuits;
- a second phase/frequency detector circuit coupled to each of said third and fourth logic circuits;
- and
- a second oscillator circuit for receiving an output of said second phase/frequency detector circuit.
Dependencies are inferred from the claim text.