Voltage level translator circuit
AssigneeCypress Semiconductor Corporation
InventorsGary W. Green, Mathew R. Arcoleo, Piyush Sevalia
Life of this patent
Estimating the term…
Loading patent…
AssigneeCypress Semiconductor Corporation
InventorsGary W. Green, Mathew R. Arcoleo, Piyush Sevalia
Estimating the term…
A method of limiting or translating the voltages of input signals, and of generating output signals such that the input's high state and low state differ by a different voltage than the output's high and low state. The present invention also teaches a system comprising a level translator circuit having level translators controlled by an operational amplifier or by a Zener diode that regulates the voltage level on one side of the translators, the other side of the translators being regulated by an external power supply. The operational amplifier or Zener diode, in some embodiments of the present invention, ensures that the second side of the level translators are limited to a given reference voltage. Often, a resistor is connected to the Zener diode or to the output of the operational amplifier, and in some embodiments a resistor-capacitor network removes higher-frequency components from the voltage supply. The invention includes a system level embodiment, in which the voltage level translators protect a memory and bus from voltage levels that would otherwise cause damage.
A method of limiting the voltages of input signals, and of generating output signals with voltages less than or equal to a desired voltage limit, comprising the steps of:
A method of limiting the voltages of input signals, and of generating output signals with voltages less than or equal to a desired voltage limit, comprising the steps of:
A voltage level translator circuit, for limiting an input signal to a desired voltage limit, comprising:
A voltage level translator circuit, for limiting an input signal to a desired voltage limit, comprising:
A level translator circuit comprising at least one level translator supplying a plurality of output voltages and receiving a plurality of input voltages, wherein the level translator receives a control voltage regulated by a Zener diode.
A level translator circuit, comprising:
Dependencies are inferred from the claim text.