US 5,691,559 AGranted

Semiconductor devices with load elements

AssigneeSeiko Epson Corporation

InventorMasakazu Kimura

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Abstract

A semiconductor device having an integrated circuit with high density load elements in memory cells forming a memory array wherein the load elements are either of the active (e.g., TFTs) or passive (e.g., resistance) type and designed so that the connection path between these elements and active element domains is extended to be longer within the same or smaller scale of the memory cell configuration. For this purpose, the connection path may be made to meander to provide for greater length, i.e., extend in one direction and then another within a single memory cell configuration. This further creates additional space for extending the resistance value of the active or passive load element which, in turn, permits a reduction in drain current, i.e., current consumption, during operational conditions of the memory cells or other circuits. The design further provides for improved mask alignment accuracy since the load element is completely constructed within a planar extent of the memory cell so that predetermined lengths of the element and predetermined, desired resistance levels can be achieved and maintained without concern for resistance level changes due to subsequent integrated circuit processing and contaminate migration.

Claims3

Dependent claims

A semiconductor device having a MISFET and a load element in a cell confined to a cell area, the cell area having edges, said device comprising:

a substrate having an impurity diffusion region forming part of said MISFET;
a power supply line at one edge of the cell area;
a gate electrode of said MISFET disposed on said substrate;
a second electrode formed on, and at least partially insulated from, said substrate and contacting said impurity diffusion region;
a first insulating layer covering said second electrode and provided with a first contact hole which exposes a contact region of said second electrode;
a first conductive layer formed on said first insulating layer and connected to said contact region of said second electrode via said first contact hole;
a second insulating layer covering said first conductive layer and provided with a second contact hole which is laterally spaced from said first contact hole and exposes a contact region of said first conductive layer, at least a portion of said second contact hole being located directly above said gate electrode;
and
a second conductive layer disposed above said second insulating layer and connected to said contact region of said first conductive layer via said second contact hole, said second conductive layer extending from said second contact hole to said power supply line, wherein
said second conductive layer forms at least a portion of said load element.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/308,777Filed 19 Sep 1994 · continuation
Priority: JP 63-28468610 Nov 1988
Granted: 25 Nov 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10B 10/00
Static random access memory [sram] devices
H10B 10/125
Comprising a MOSFET load element: the MOSFET being a thin film transistor [TFT]
H10B 10/15
Static random access memory [SRAM] devices: comprising a resistor load element
Y10S 257/903
Active solid-state devices, e.g. transistors, solid-state diodes: fET configuration adapted for use as static memory cell

Family

Serial410,936Parent of this continuation-in-part · filed 22 Sep 1989
US 5,107,322 AParent of this continuation-in-part · filed 22 Sep 1989
Serial871,871Parent of this continuation · filed 20 Apr 1992
US 5,349,206 AParent of this continuation · filed 20 Sep 1994
US 5,691,559 AThis patent

From the US filing history. Foreign family members aren’t listed.