Multi-channel tone generation apparatus with multiple CPU's executing programs in parallel

A digital microcomputer comprising:

• a main CPU for executing a main program to process various control inputs and an interrupt routine incorporated therein to generate a plurality of tone waveform signals;
• at least one sub CPU for executing a program for executing a process to generate a plurality of tone waveform signals assigned by said main program of said main CPU;
• interrupt signal generating means for generating an interrupt signal each time a predetermined time elapses;
• main-CPU mode control means for switching a mode of said main CPU to interrupt said main program being executed by said main CPU and execute said interrupt routine in response to said interrupt signal, and for switching said mode of said main CPU back to a mode to execute said main program again upon completion of execution of said interrupt routine;
• sub-CPU mode control means for switching a mode of said sub CPU from an idle status to a mode to execute said program of said sub CPU in response to said interrupt signal, and for rendering said sub CPU again in said idle status upon completion of execution of said program of said sub CPU;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said main CPU by executing said interrupt routine in said main CPU and said program in said sub CPU, without using either a tone generating circuit or discrete oscillators.

A digital microcomputer comprising:

• a main CPU for executing a main program to process various control inputs and an interrupt routine to generate a plurality of tone waveform signals;
• at least one sub CPU having an internal memory;
• interrupt signal generating means for generating a timer interrupt signal each time a predetermined time elapses;
• main-CPU mode control means for switching a mode of said main CPU to an interrupt mode in which the main program executed by said main CPU is interrupted and said main CPU is caused to execute the interrupt routine in response to said timer interrupt signal, and for switching said mode of said main CPU back to an execute mode to restart said interrupted main program and execute said main program upon completion of execution of said interrupt program;
• sub-CPU mode control means for switching a mode of said sub CPU from an idle status mode to a an execute mode for executing a program of said sub CPU in response to said timer interrupt signal to generate a plurality of tone waveform signals, and for switching said mode of said sub CPU back to said idle status mode upon completion of execution of said program of said sub CPU;
• sub-CPU mode signal generating means, provided in said sub CPU-mode control means, for generating a signal representing the idle status mode;
• sub-CPU mode detecting means, provided in said main CPU, for detecting said mode of said sub CPU upon reception of said mode-representing signal from said sub-CPU mode signal generating means;
• sub-CPU access means, provided in said main CPU, for accessing the internal memory of said sub CPU while said sub CPU is detected to be in said idle status mode by said sub-CPU mode detecting means;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said main CPU by executing said interrupt routine in said main CPU and said program in said sub CPU, without using either a tone generating circuit or discrete oscillators.

A digital microcomputer, comprising:

• a first CPU for executing a program to generate a plurality of tone waveform signals;
• a second CPU with an internal memory for executing a program to generate a plurality of tone waveform signals;
• said first CPU including access-request signal generating means for generating an excess request signal when executing a command to access the internal memory of said second CPU;
• said second CPU including operation interrupt means for interrupting an operation being executed by said second CPU so as to set said internal memory free for said first CPU in response to said access request signal;
• said first CPU further including access executing means for executing an access operation to access said internal memory of said second CPU when said internal memory is rendered free for said first CPU, and access end signal generating means for generating an access end signal when said access executing means completes said access operation;
• said second CPU further comprising operation restart means for restarting said interrupted operation in response to said access end signal;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said first CPU by executing said programs in said first CPU and said second CPU, without using either a tone generating circuit or discrete oscillators.

A digital microcomputer having a first CPU and a second CPU including an internal memory, comprising:

• first clock generating means for generating a clock signal to enable said first CPU;
• said first CPU executing a program to generate a plurality of tone waveform signals;
• second clock generating means for generating a clock signal to enable said second CPU;
• said second CPU executing a program to generate a plurality of tone waveform signals;
• clock stop means for disabling said second clock generating means in response to an access request signal output from said first CPU when said first CPU executes a command to access the internal memory of said second CPU, thereby interrupting an operation being executed by said second CPU and setting said second CPU in an idle state;
• access-path switching means for switching an access path to said internal memory of said second CPU from a first access path to be used by said second CPU to a second access path to be used by said first CPU, in response to said access request signal;
• access executing means for executing an access operation to access said internal memory of said second CPU from said first CPU through said second access path switched by said access-path switching means;
• access-path restoring means for switching said access path to said internal memory from said second access path to be used by said first CPU to said first access path to be used by said second CPU, in response to an access end signal from said first CPU, representing an end of said access operation;
• clock restarting means for restarting said second clock generating means in response to said access end signal to thereby restart said interrupted operation in said second CPU from said idle state;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said first CPU by executing said programs in said first and second CPUs, without using either a tone generating circuit or discrete oscillators.

A digital information processing apparatus for use in an electronic musical instrument, comprising:

• one main CPU;
• at least one sub-CPU;
• and
• means for permitting said main CPU and said sub CPU to execute respective programs for taking a share of executing individual portions of a process of generating tone waveform signals, wherein said main CPU executes a program of a first process, which is a first portion of a multiple tone signal generating process, and said sub CPU executes a program of a second process which is the remaining portion of said multiple tone signal generating process in accordance with a result of said process executed by said main CPU, and wherein said tone waveform signals are generated and output in parallel from said main CPU, without using either a tone generating circuit or discrete oscillators.

A digital information processing apparatus having one main CPU and at least one sub CPU to be controlled by said main CPU,

• said main CPU comprising:
• MCPU program storage means for storing a process program representing a predetermined process to generate a plurality of tone waveform signals;
• MCPU address control means for controlling an address of said MCPU program storage means;
• MCPU data storage means for storing data necessary for said predetermined process;
• MCPU arithmetic operation means coupled to said MCPU program storage means and to said MCPU data storage means for executing an arithmetic operation;
• and
• MCPU operation control means for decoding individual commands of said program stored in said MCPU program storage means and controlling operations of said MCPU address control means, said MCPU data storage means and said MCPU arithmetic operation means;
• said at least one sub CPU comprising:
• SCPU program storage means for storing a process program representing a predetermined process to generate a plurality of tone waveform signals;
• SCPU address control means for controlling an address of said SCPU program storage means;
• SCPU data storage means for storing data necessary for said predetermined process;
• SCPU arithmetic operation means coupled to said SCPU program storage means and to said SCPU data storage means for executing an arithmetic operation;
• and
• SCPU operation control means for decoding individual commands of said program stored in said SCPU program storage means and controlling operations of said SCPU address control means, said SCPU data storage means and said SCPU arithmetic operation means;
• and
• said digital information processing apparatus further comprising:
• parallel-process start signal generating means for generating a parallel-start signal;
• and
• CPU-mode control means for controlling mode switching so as to switch a mode of said one main CPU and said at least one sub CPU to an sub CPU to an execution mode for a predetermined process allotted to said CPUs, in response to said parallel-process start signal, thereby ensuring said one main CPU and said at least one sub CPU realize parallel processing;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said main CPU by executing said programs in said main CPU and in said sub CPU, without using either a tone generating circuit or discrete oscillators.

A digital information processing apparatus having a plurality of CPUs including one main CPU and at least one sub CPU to be controlled by said main CPU,

• said main CPU comprising:
• MCPU program storage means for storing a process program representing a predetermined process to generate a plurality of tone waveform signals;
• MCPU address control means for controlling an address of said MCPU program storage means;
• MCPU data storage means for storing data necessary for said predetermined process;
• MCPU arithmetic operation means coupled to said MCPU program storage means and to said MCPU data storage means for executing an arithmetic operation;
• and
• MCPU operation control means for decoding individual commands of said program stored in said MCPU program storage means and controlling operations of said MCPU address control means, said MCPU data storage means and said MCPU arithmetic operation means;
• said at least one sub-CPU comprising:
• SCPU program storage means for storing a process program representing a predetermined process to generate a plurality of tone waveform signals;
• SCPU address control means for controlling an address of said SCPU program storage means;
• SCPU data storage means for storing data necessary for said predetermined process;
• SCPU arithmetic operation means coupled to said SCPU program storage means and to said SCPU data storage means for executing an arithmetic operation;
• and
• SCPU operation control means for decoding individual commands of said program stored in said SCPU program storage means and controlling operations of said SCPU address control means, said SCPU data storage means and said SCPU arithmetic operation means;
• and
• said digital information processing apparatus further comprising:
• a common read-only memory means shared by said plurality of CPUs;
• a plurality of address latch means for respectively latching addresses for said common read-only memory means output from said plurality of CPUs;
• address select means, provided between said plurality of address latch means and said common read-only memory means, for selecting an address output from any of said plurality of address latch means;
• a plurality of output-data latch means, provided between said common read-only memory means and said plurality of CPUs, for selectively latching data output from said common read-only memory means to distribute said data to a desirable one of said plurality of CPUs;
• control means for, in response to access request signals output from two or more of said plurality of CPUs when simultaneously requesting access to said common read-only memory means, controlling said address select means, said common read-only memory means and said plurality of output-data latch means in a sequence so as to execute an actual access operation to said common read-only memory means for each of said two or more CPUs requesting said address without causing any overlapping;
• and
• wherein said plurality of tone waveform signals are generated and output in parallel from said main CPU by executing said programs in said main and in said sub CPUs, without using either a tone generating circuit or discrete oscillators.