US 5,691,248 AGranted

Methods for precise definition of integrated circuit chip edges

AssigneeInternational Business Machines Corporation

InventorsJohn Edward Cronin, Wayne John Howell, Howard Leo Kalter, Patricia Ellen Marmillion, Anthony Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt

Life of this patent

Estimating the term…

patentgrep

Loading patent…

Abstract

Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Claims23

Dependent claims

A method for use in defining at least one edge of an integrated circuit ("IC") chip, said IC chip comprising part of a wafer having a first planar main surface and a second planar main surface, a portion of said second planar main surface of said wafer being parallel to a planar main surface of said IC chip, said method comprising the steps of:

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer, said first trench having a bottom;
(b) filling said first trench with an insulating material;
(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;
(d) forming a second trench through said transfer metal layer and coincident with said first trench;
and
(e) polishing said planar main surface of said IC chip toward said bottom of said first trench and toward said first planar main surface of said wafer to thin said IC chip such that said first trench and said second trench define the at least one edge of the IC chip and such that an end of a transfer metal lead of the transfer metal layer is aligned with the at least one edge of the IC chip.

3 more elements

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer;
(b) forming two insulating layers within the first trench, a first insulating layer of said two insulating layers having a surface comprising the at least one edge of said IC chip, a second insulating layer of the two insulating layers comprising a removable kerf region;
(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;
(d) forming a second trench through said transfer metal layer and coincident with said surface of said first insulating layer comprising the at least one edge of the IC chip such that the at least one edge of the IC chip is further defined and such that an end of a transfer metal lead of said transfer metal layer is aligned with the at least one edge of the IC chip;
and
(e) thinning said IC chip from said planar main surface thereof and toward said first planar main surface of said wafer to facilitate separation of said IC chip from said wafer and removal of said removable kerf region to define the at least one edge of the IC chip.

3 more elements

A method for defining at least one edge of an integrated circuit ("IC") chip, said IC chip comprising part of a wafer having a first planar main surface and a second planar main surface, a portion of said second planar main surface of said wafer being parallel to a planar main surface of said IC chip, said method comprising the steps of:

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer, said first trench defining the at least one edge of said IC chip;
(b) forming an insulating layer within said first trench;
(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;
(d) forming a second trench through said transfer metal layer and coincident with said outer sidewalls of said pair of first trenches such that the at least one edge of the IC chip is further defined and such that ends of transfer metal leads of said transfer metal layer are aligned with the at least one edge of the IC chip;
(e) dicing said wafer along a path substantially parallel to said first trench and outside of said IC chip to form a kerf region between said first trench and said path;
and
(f) removing said kerf region and said insulating layer to form the at least one edge of said IC chip.

4 more elements

Dependencies are inferred from the claim text.