Method of manufacturing BICMOS integrated circuits

A method of manufacturing integrated circuits having both bipolar and CMOS devices on the same chip, the method comprising the steps of:

• providing a P- silicon substrate appropriately doped to provide an N- buried layer region for at least one vertical PNP device and to provide N+ buried layer regions for at least one PMOS device and at least one vertical NPN device;
• providing a P+ region in the N- buried layer region and in the P-substrate for at least one NMOS device;
• providing an N- epitaxial layer over the P+, N+ and N- regions;
• providing a P well region in the N- epitaxial layer of the NMOS device extending to the P+ region and in a first part of the N- epitaxial layer of the vertical PNP device extending to the P+ region;
• providing an N base region in a second part of the N- epitaxial layer of the vertical PNP device;
• providing a P base region in a first part of the N- epitaxial layer of the vertical NPN device;
• simultaneously providing:
• an N+ region on part of the P base region of the vertical NPN device to form the emitter thereof,
• an N+ region on a second part of the N- epitaxial layer of the vertical NPN device to form the collector contact thereof,
• N+ regions on first and second parts of the P well region of the NMOS device to form the source and drain thereof, and
• an N+ region on the N base region of the vertical PNP device to form the base contact thereof;
• and
• simultaneously providing:
• P+ regions on the P well and N base regions of the vertical PNP device to form the collector and emitter contacts thereof,
• P+ regions on first and second parts of the N- epitaxial layer of the PMOS device to form the source and drain thereof, and
• a P+ region on part of the P base region of the vertical NPN device to form the base contact thereof.