Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers

A method of forming a pair of field effect transistors having different thickness gate dielectric layers comprising the following steps:

• providing a first region on a substrate for formation of a first field effect transistor having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness;
• providing the first gate dielectric layer and a first conductive gate layer over the first and second regions;
• patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region;
• after defining the first gate, providing an insulating dielectric layer over the first region and the second region;
• providing a layer of device component material outwardly of the insulating dielectric layer;
• providing a layer of photoresist over the layer of device component material, the photoresist layer being patterned for definition of a device component from the device component material in the first region and leaving the second region outwardly exposed;
• etching the layer of device component material to define the device component, and stripping the device component material and the first conductive layer using the patterned photoresist layer as a common mask for such etching and stripping;
• after stripping the device component material, the first conductive layer and the first gate dielectric layer from the second region, providing the second gate dielectric layer and a second conductive gate layer over the second region;
• and
• patterning the second conductive layer in the second region to define a second gate of the second field effect transistor in the second region.

A method of forming a pair of field effect transistors having different thickness gate dielectric layers comprising the following steps:

• providing a first region on a substrate for formation of a first field effect transistor having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness;
• providing the first gate dielectric layer and a first conductive gate layer over the first and second regions;
• patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region;
• after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region;
• after stripping the first conductive layer and the first gate dielectric layer from the second region, providing the second gate dielectric layer and a second conductive gate layer over the first region and the second region;
• and
• patterning the second conductive layer to, a) define a second gate of the second field effect transistor in the second region, and b) define a capacitor dielectric layer comprising the second gate dielectric layer and a capacitor plate of a capacitor within the first region.

A method of forming an SRAM cell comprising the following steps:

• providing a first region on a bulk semiconductor substrate for formation of an NMOS access transistor and an NMOS pull down transistor having a common first gate dielectric layer of a first thickness and providing a second region on the semiconductor substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness;
• providing the first gate dielectric layer and a first conductive gate layer over the first and second regions;
• patterning the first conductive layer to define a gate of the NMOS access transistor and a gate of the NMOS pull down transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region;
• after defining the access transistor gate and the pull down transistor gate, providing an insulating dielectric layer over the first region and the second region;
• etching the insulating dielectric layer to form a contact opening in the first region to the pull down transistor gate and to outwardly expose the first conductive gate layer in the second region;
• providing a layer of semiconductive material outwardly of the insulating dielectric layer and within the contact opening in electrical connection with the pull down transistor gate;
• providing a layer of photoresist over the layer of semiconductive material, the photoresist layer being patterned for definition of an SRAM load resistor from the semiconductive material layer in the first region and leaving the second region outwardly exposed;
• etching the layer of semiconductive material to define the load resistor shape and stripping the first conductive layer from the second region using the patterned photoresist layer as a common mask for such etching and stripping;
• after defining the load resistor shape, stripping the semiconductive material, the first conductive layer and the first gate dielectric layer from the second region;
• after stripping the semiconductive material, the first conductive layer and the first gate dielectric layer from the second region, providing the second gate dielectric layer and a second conductive gate layer over the first region and the second region;
• and
• patterning the second conductive layer to, a) define a second gate of the second field effect transistor in the second region, and b) define a capacitor dielectric layer comprising the second gate dielectric layer and a capacitor plate of a capacitor within the first region.