Programmable serializer using multiplexer and programmable address counter for providing flexiblity in scanning sequences and width of data

A serializer for converting parallel pixel data into serial pixel data, comprising:

• a multi-bit data input port for receiving the parallel pixel data from a video memory;
• a multi-bit data output port for outputting selected pixel data;
• at least one multiplexer having a multiplexer output connected to said output port, an address input, and a plurality of data input channels having addresses, each of the plurality of data input channels being connected to a corresponding bit of said input port, at least one data input channel being coupled to the multiplexer output when the corresponding address of the said at least one data input channel is applied to said address input;
• at least one programmable address counter corresponding to said at least one multiplexer for generating a sequence of multiplexer data input addresses for input into said multiplexer address input, said counter including a storage device for storing an initial address value, an address increment value and a count value, said initial address value representing the multiplexer data channel that is to be initially coupled to the multiplexer output, said address increment value representing the increment that must be added to a current multiplexer data channel address so as to produce a next multiplexer data channel address, the current multiplexer data channel address initially being determined by the initial address value, said count value representing the number of multiplexer addresses that must be generated by said at least one programmable counter prior to said counter restarting the sequence at said initial address value;
• and
• means for changing the initial address, address increment and count values stored in said storage device of said programmable counter.

A serializer for converting parallel pixel data into serial pixel data, comprising:

• a multi-bit data input port for receiving the parallel pixel data from a video memory, the parallel pixel data being defined by groups of bits wherein each pixel is represented by at least one of said group of bits;
• a multi-bit data output port for outputting selected data from at least one of said groups of bits;
• at least one multiplexer having a multiplexer output connected to said output port, an address input, and a plurality of groups of data input channels, each group of data input channels having an address, each group of data input channels being connected to a corresponding group of bits of said input port, one of said groups of data input channels being coupled to the multiplexer output when the corresponding address of said one of said groups of data input channels is applied to said address input;
• at least one programmable address counter corresponding to said at least one multiplexer for generating a sequence of multiplexer data input addresses for input into said multiplexer address input, said counter including a storage device for storing an initial address value, an address increment value and a count value, said initial address value representing the group of multiplexer data input channels initially coupled to the multiplexer output, said address increment value representing the increment that must be added to a current address so as to produce a next address, the current address initially being determined by the initial address value, said count value representing the number of addresses that must be generated by said at least one programmable counter prior to said counter restarting the sequence of said initial address value;
• and
• means for changing the initial address, address increment and count values stored in said storage device of said programmable counter.