Method and apparatus for providing low power control of peripheral devices using the register file of a microprocessor

A data processing system comprising:

• a central processing unit (CPU) located on an integrated circuit;
• a data bus coupled from the CPU to external terminals of the integrated circuit for communicating with peripherals external to the CPU;
• a plurality of registers located on the integrated circuit;
• an internal bus coupling the CPU to the plurality of registers so that read and write operations can be performed directly to the plurality of registers via the internal bus without using the data bus, the internal bus being located totally within the integrated circuit;
• a plurality of input terminals of the integrated circuit coupled to a status register wherein the status register is one register within the plurality of registers, the status register being capable of being read by the CPU;
• a plurality of output terminals of the integrated circuit coupled to a control register wherein the control register is one register within the plurality of register, the control register being capable of being written with low power control information by the CPU,
• wherein a first CPU instruction is used to access the data bus and a second CPU instruction different from the first CPU instruction is used to access the control register and the status register;
• and
• a plurality of peripheral devices having output terminals coupled to the plurality of input terminals of the integrated circuit and having input terminals coupled to the plurality of output terminals of the integrated circuit, the control register and status register using the plurality of input terminals and plurality of output terminals of the integrated circuit to control a low power mode of the plurality of peripheral devices.

A method for controlling a low power mode of operation of a plurality of peripheral devices coupled to a microprocessor, the method comprising the steps of:

• providing a plurality of low power control signals from a central processing unit of the microprocessor to a control register internal to the microprocessor via a first internal bus that is internal to the microprocessor, the first internal bus being separate from a data bus used by the microprocessor to communicate with external memory;
• providing the plurality of low power control signals to a plurality of output terminals from the control register within the microprocessor;
• communicating the plurality of low power control signals from the plurality of output terminals to the plurality of peripheral devices so that at least one of the peripheral devices in the plurality of peripheral devices enters into a low power mode in response to the plurality of low power control signals;
• communicating a plurality of low power status signals from the plurality of peripheral devices to a plurality of input terminals of the microprocessor;
• providing the plurality of low power status signals from the plurality of input terminals to a status register internal to the microprocessor;
• and
• providing the plurality of low power status signals from the status register to the central processing unit of the microprocessor so that the central processing unit is able to monitor the low power status of the plurality of peripheral devices.

A data processing system formed on an integrated circuit comprising:

• a central processing unit (CPU);
• a plurality of registers coupled to the CPU via an internal bus that is not directly accessible outside of the integrated circuit;
• and
• a plurality of data terminals on an external portion of the integrated circuit wherein a data bus couples the plurality of data terminals to the CPU,
• wherein a first opcode is executed by the CPU to access the plurality of registers via the internal bus and a second opcode is executed to access the data bus wherein the first opcode is a different opcode from the second opcode, and wherein a first register in the plurality of registers is coupled to a plurality of output terminals of the external portion of the integrated circuit and a second register in the plurality of registers is coupled to a plurality of input terminals of the external portion of the integrated circuit, and
• wherein the first register and the second register are used to provide low power control information to a plurality of peripheral devices and receive low power status information from the plurality of peripheral devices, respectively, so that a power consumption of the plurality of peripheral devices is controlled.