Conditional processor operation based upon result of two consecutive prior processor operations

A method of conditional data processing operation implemented in three consecutive instructions consisting of the steps of:

• (1) storing at least one instance of a set of three consecutive instructions forming an OR conditional sequence;
• (2) in response to a first instruction of an instance of said set of three consecutive instructions forming an OR conditional sequence
• performing a first arithmetic/logical operation forming a first result, and
• setting a first condition in either a first state or a second state dependent upon said first result of said first arithmetic/logical operation;
• (3) in response to a second instruction of said instance of said set of three consecutive instructions forming an OR conditional sequence
• performing a second arithmetic/logical operation forming a second result if said first condition is in said second state and not performing said second arithmetic/logical operation if said first condition is in said first state, and
• setting said first condition in either said first state or said second state dependent upon said second result of said second arithmetic/logical operation if said second arithmetic/logical operation was performed;
• and
• (4) in response to a third instruction of said instance of said set of three consecutive instructions forming an OR conditional sequence
• performing a third operation conditional upon said first condition being in said first state, whereby said third operation is performed if either said result of said first arithmetic/logical operation or said result of said second arithmetic/logical operation set said first condition in said first state.

A method of conditional data processing operation implemented in three consecutive instructions consisting of the steps of:

• (1) storing at least one instance of a set of three consecutive instructions forming a MIXED conditional sequence;
• (2) in response to a first instruction of a instance of said set of three consecutive instructions forming a MIXED conditional sequence
• performing a first arithmetic/logical operation forming a first result, and
• setting each of a set of a plurality conditions in either a first state or a second state dependent upon said first result of said first arithmetic/logical operation;
• (3) in response to a second instruction of said instance of said set of three consecutive instructions forming a MIXED conditional sequence
• performing a second arithmetic/logical operation forming a second result, and
• setting each of said set of conditions in either said first state or said second state dependent upon said second result of said second arithmetic/logical operation except that changing of a predetermined first condition of said set of conditions is inhibited;
• and
• (4) in response to a third instruction of said instance of said set of three consecutive instructions forming a MIXED conditional sequence
• performing a third operation conditional upon a predetermined combination of said predetermined first condition of said set of conditions and at least one other condition of said set of conditions, whereby said third operation is performed only if said predetermined combination of said predetermined first condition of said set of conditions and said at least one other condition of said set of conditions is satisfied.

A data processing apparatus comprising:

• a plurality of data registers;
• a status register storing at least one status bit;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming an AND conditional sequence;
• an instruction decode logic connected to said plurality of data registers, said status register, said arithmetic logic unit and said instruction memory, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of said set of three consecutive instructions forming an AND conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting said at least one status bit in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit,
• said instruction decode logic in response to a second instruction of said instance of said set of three consecutive instructions forming an AND conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register only if said at least one status bit in said status register have a predetermined state, and
• setting said at least one status bit in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit, and
• said instruction decode logic in response to a third instruction of said instance of said set of three consecutive instructions forming an AND conditional sequence controls performance of a third operation only if said at least one status bit in said status register has said predetermined state.

An data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a plurality of data registers;
• a status register storing at least one status bit;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming an OR conditional sequence;
• and
• an instruction decode logic connected to said plurality of data registers, said status register and said arithmetic logic unit, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of a set of three consecutive instructions forming an OR conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting said at least one status bit in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit,
• said instruction decode logic in response to a second instruction of said instance of a set of three consecutive instructions forming an OR conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register only if said at least one status bit in said status register has a first predetermined state, and
• setting said at least one status bit in said status register to said first state or said second state corresponding to said result of said arithmetic logic unit, and
• said instruction decode logic in response to a third instruction of said instance of a set of three consecutive instructions forming an OR conditional sequence controls performance of a third operation only if said at least one status bit in said status register has a second predetermined state inverse to said first predetermined state.

An data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a plurality of data registers;
• a status register storing at least one status bit;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming an AND conditional sequence;
• and
• an instruction decode logic connected to said plurality of data registers, said status register, said arithmetic logic unit and said instruction memory, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of said set of three consecutive instructions forming an AND conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting said at least one status bit in said status register to a first state or a second state corresponding
• to said result of said arithmetic logic unit, said instruction decode logic in response to a second instruction of said instance of said set of three consecutive instructions forming an AND conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register only if said at least status bit in said status register has a first predetermined state, and
• setting said at least one status bit in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit, and
• said instruction decode logic in response to a third instruction of said instance of said set of three consecutive instructions forming an AND conditional sequence controls performance of a third operation only if said at least one status bit in said status register has said first predetermined state.

A data processing apparatus comprising:

• a plurality of data registers;
• a status register storing a plurality of status bits;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming a MIXED conditional sequence;
• and
• an instruction decode logic connected to said plurality of data registers, said status register and said arithmetic logic unit, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of a set of three consecutive instructions forming a MIXED conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting each of said plurality of status bits in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit,
• said instruction decode logic in response to a second instruction of said instance of a set of three consecutive instructions forming a MIXED conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register, and
• setting each of said plurality of status bits in said status register to said first state or said second state corresponding to said result of said arithmetic logic unit except that changing a predetermined set of status bits is inhibited,
• said instruction decode logic in response to a third instruction of said instance of a set of three consecutive instructions forming a MIXED conditional sequence controls performance of a third operation only if said predetermined set of status bits and at least one other of said plurality of status bits have a predetermined combination.

A data processing apparatus comprising:

• a plurality of data registers;
• a status register storing at least one status bit;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming an OR conditional sequence;
• and
• an instruction decode logic connected to said plurality of data registers, said status register, said arithmetic logic unit and said instruction memory, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of a set of three consecutive instructions forming an OR conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting said at least one status bit in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit,
• said instruction decode logic in response to a second instruction of said instance of a set of three consecutive instructions forming an OR conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register only if said at least one status bit in said status register has a first predetermined state, and
• setting said at least one status bit in said status register to said first state or said second state corresponding to said result of said arithmetic logic unit, and
• said instruction decode logic in response to a third instruction of said instance of a set of three consecutive instructions forming an OR conditional sequence controls performance of a third operation only if said at least one status bit in said status register has a second predetermined state inverse to said first predetermined state.

An data processing system comprising:

• an data system bus transferring data and addresses;
• a system memory connected to said data system bus, said system memory storing data and transferring data via said data system bus;
• an data processor circuit connected to said data system bus, said data processor circuit including
• a plurality of data registers;
• a status register storing at least one status bit;
• an arithmetic logic unit having first and second inputs and an output coupled to said plurality of data registers, said arithmetic logic unit performing an arithmetic or logical operation upon data received at said first and second input and generating a result at said output;
• an instruction memory storing instructions, said stored instructions including at least one instance of a set of three consecutive instructions forming a MIXED conditional sequence;
• and
• an instruction decode logic connected to said plurality of data registers, said status register and said arithmetic logic unit, said instruction decode logic controlling said plurality of data registers, said status register and said arithmetic logic unit in response to a received instruction, said instruction decode logic in response to a first instruction of an instance of a set of three consecutive instructions forming a MIXED conditional sequence
• controlling said arithmetic logic unit to form a first combination of inputs from designated source data registers and store said result in a designated destination data register, and
• setting each of said plurality of status bits in said status register to a first state or a second state corresponding to said result of said arithmetic logic unit,
• said instruction decode logic in response to a second instruction of said instance of a set of three consecutive instructions forming a MIXED conditional sequence
• controlling said arithmetic logic unit to form a second combination of input from designated source data registers and store said result in a designated destination data register, and
• setting each of said plurality of status bits in said status register to said first state or said second state corresponding to said result of said arithmetic logic unit except that changing a predetermined set of status bits is inhibited,
• said instruction decode logic in response to a third instruction of said instance of a set of three consecutive instructions forming a MIXED conditional sequence controls performance of a third operation only if said predetermined set of status bits and at least one other of said plurality of status bits have a predetermined combination.