Computer bus utilization determination apparatus
AssigneeCompaq Computer Corporation
InventorJames M. Mann
Life of this patent
Estimating the term…
Abstract
Circuitry for monitoring the idle periods on the EISA bus and a program using this known value to determine percentage utilization of the EISA bus. A counter is used to count the number of synchronizing clock periods during which the EISA bus is idle. To determine if the EISA bus is idle, certain logic monitors the EISA bus signals and the arbiter activity to determine if cycles are actually occurring. If so, the EISA bus is not idle and the counter is not incremented. If there is no activity, the counter increments on each BCLK clock. The computer system periodically reads this counter. The computer system determines the interval between read operations of the counter and uses this interval in combination with the counter value and BCLK signal rate to determine the percentage utilization.
Claims8
A system for determining utilization of a bus on which a plurality of different cycles may be run, the cycles having a length which is a multiple of a synchronizing clock, and which may be controlled by a number of sources, comprising:
- means for determining if the bus is idle;
- means for counting the number of synchronizing clock periods wherein the bus is determined to be idle;
- means for periodically reading said means for counting and obtaining a counter value;
- means for determining the time between said periodic reading of said means for counting;
- and
- means for determining a bus utilization value utilizing a ratio of said counter value times the synchronizing clock period to said time between periodic reading.
Dependencies are inferred from the claim text.