Clock circuits for synchronized processor systems having clock generator circuit with a voltage control oscillator producing a clock signal synchronous with a master clock signal

A method for providing clock signals synchronized to a master clock signal for each of at least a pair of processing elements, including the steps of:

• providing at least one of the pair of processing elements with a master oscillator circuit to produce the master clock signal;
• providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals for such processing element, the clock generator circuit including:
• an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal,
• a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal,
• and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage;
• and
• coupling the master oscillator circuit of a one of the pair of processing elements to provide the master clock signal for the clock generator o the pair of processing elements.

A method for providing clock signals synchronized to a master clock signal for each of at least a pair of synchronous processing elements, including the steps of:

• providing each of the pair of processing elements with a clock generator circuit coupled to receive the master clock signal to produce therefrom the synchronized clock signals, the clock generator circuit including:
• an oscillator circuit responsive to a phase voltage to produce a first clock signal that is synchronous with the master clock signal,
• a counter circuit coupled to receive the first clock signal produce a number of divisions of the first clock signal forming the synchronized clock signals and a replica of the master clock signal,
• and a phase compare means coupled to receive the master clock signal and the replica of the master clock signal to produce the phase voltage;
• providing each of the pair of processing elements with a master oscillator circuit to produce a clock signal;
• and
• coupling the master oscillator circuit of a one of the pair of processing elements to provide the clock signal as the master clock signal to the clock generator circuits for each of the pair of processing elements.

A processing system having at least a pair of processor units formed to be physically separate from one another, each of the processor units having a clock generator circuit operating to produce a plurality of clock signals synchronized to a master clock signal provided by a master clock generator, a method of providing the master clock signal to the clock generator circuit of each of the pair of processor units, including the steps of:

• providing at least one of the processor units with the master clock generator;
• coupling the master clock signal from the master clock generator to the clock generator circuit of other of the processor units that includes a first signal line;
• and
• coupling the master clock signal from the master clock generator to the clock generator of the one of the pair of processor units by a second signal line that includes an intermediate signal line that leaves the one processing unit and returns to the one processing unit to apply the master clock signal to the clock generator of the one processor unit for introducing a first delay that approximates a second delay imposed on the master clock signal coupled to the other processor unit.