Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
AssigneeUnisys Corporation
InventorsBruce E. Whittaker, David M. Kalish, Saul Barajas
Life of this patent
Estimating the term…
Abstract
A "bit-sliced" construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be "overlapped", and even operate simultaneously.
Claims3
A computer system with cache memory coupled to a system bus mean and adapted to provide coincident, simultaneous operations, said cache memory comprising a pair of like, separate, bit-sliced cache modules, each including a first and second IN-register means for storing spy address value from system bus write operation, and invalidation queue means fed, in multiplex fashion, by the outputs of said IN-register means and, in turn, feeding its output to a TAG RAM structure;
- each said TAG RAM structure being arranged and adapted to handle only on-half of the address values presented, and also arranged to enable processor operations and invalidation operations to be "overlapped", and to even operate simultaneously;
- the system comprises:
- invalidation spy control logic means for monitoring said system bus of commands that potentially modify data stored in said cache modules;
- cache gate array means for handling even and odd addresses;
- cache control logic means utilized for distinguishing between said even and odd addresses, and directing cache requests to said cache gate array means;
- said cache modules being input by first system bus means coupled via associated first spy register means, to both said first IN-registers means, and also input by second system bus mean, coupled, via associated second spy register means, to both said second IN-register means;
- wherein said first spy register means and said second spy register means are for storing the potential invalidation address that is being loaded from said invalidation spy control logic means.
A computer system with cache memory coupled to a system bus mean and adapted to provide coincident, simultaneous operations, said cache memory comprising a pair of like, separate, bit-sliced cache modules, each including a first and second IN-register means for storing spy address value from system bus write operation, and invalidation queue means fed, in multiplex fashion, by the outputs of said IN-register means and, in turn, feeding its output to a TAG RAM structure;
- each said TAG RAM structure being arranged and adapted to handle only on-half of the address values presented, and also arranged to enable processor operations and invalidation operations to be "overlapped", and to even operate simultaneously;
- the system comprises:
- invalidation spy control logic means for monitoring said system bus of commands that potentially modify data stored in said cache modules;
- cache gate array means for handling even and odd addresses;
- cache control logic means utilized for distinguishing between said even and odd addresses, and directing cache requests to said cache gate array means;
- said cache modules being input by first system bus means coupled via associated first spy register means, to both said first IN-registers means, and also input by second system bus mean, coupled, via associated second spy register means, to both said second IN-register means;
- wherein said first spy register means and said second spy register means are for storing the potential invalidation address that is being loaded from said invalidation spy control logic means;
- wherein said TAG RAM arrays and invalidation queue means comprise a pair of identical ASIC arrays.
Dependencies are inferred from the claim text.