US 5,689,679 A · Memory system and method for selective multi-level caching using a cache level code

Abstract

A selective multilevel caching method and system including a main memory and a plurality of cache memories are disclosed. The main memory and cache memories are arranged in a multilevel hierarchy: the main memory is at the lowest hierarchical level; the cache memory that is coupled directly to the central processing unit (CPU) is at the highest hierarchical level; and the remaining cache memories are coupled in the hierarchy at intermediate hierarchical levels therebetween. Each hierarchical level contains cache logic as well as a cache memory. Each cache logic responds to a cache level code that is associated with an address specified in each CPU read or write data request. The cache level code specifies the highest hierarchical level at which data associated with the data request may be written. Each cache logic uses the cache level code to determine if data will be written to the cache memory at the same hierarchical level as that cache logic. Each CPU write request further includes a cache control code. The cache control code indicates whether each cache level is designated as a write-allocate cache level. Each cache logic responds also to the cache control code to further determine if data will be written to the cache memory at the same hierarchical level as that cache logic.

Claims26

Dependent claims

A memory system for coupling to a central processor, which issues a data request having a specified address to be accessed, the memory system comprising;

a main memory;
cache levels coupled between the main memory and the central processor in a multilevel hierarchy, each of the cache levels having a cache memory;
means, coupled to the processor, for identifying a cache level code associated with the data request, the cache level code indicating a hierarchical level in the multilevel hierarchy;
and
means for determining from the cache level code whether or not data associated with the specified address can be written to the cache memory at each of the cache levels.

2 more elements

A memory system coupled to a central processor, the central processor issuing a data write request having new data to be written over old data at a specified address, the memory system comprising;

a main memory;
a plurality of cache levels coupled between the main memory and the central processor in a multilevel hierarchy, one of the cache levels being coupled to the central processor at a highest hierarchical level in the multilevel hierarchy, the main memory being at a lowest hierarchical level, each of the cache levels having a cache memory;
and
means, responsive to the data write request and coupled to the central processor, for identifying a cache control code associated with the data write request, the cache control code indicating whether each of the cache levels is designated for write-allocation;
and
cache logic at each of the cache levels, the cache logic at each of the cache levels being coupled to the cache memory at the same cache level as that cache logic, the cache logic at each of the cache levels responding to the data write request by issuing a miss signal and the specified address to the next lower hierarchical level when the specified address is not stored in the cache memory to which that cache logic is coupled,
the cache logic at a particular cache level that is at a lower hierarchical level than the highest hierarchical level responding to the data write request by passing the old data up to the next higher hierarchical level when the specified address is found in the cache memory coupled to that cache logic and a miss signal has issued from a next higher hierarchical level,
the cache logic at a particular cache level that receives old data from a lower hierarchical level writing the old data to the cache memory coupled to that cache logic when the particular cache level that receives old data is designated for write allocation as indicated by the cache control code.

5 more elements

A method for selectively caching data in a computer system having a central processor and a main memory, the method comprising the steps of:

coupling a plurality of cache levels in a multilevel hierarchy between the central processor and the main memory, one of the cache levels being coupled to the central processor at a highest hierarchical level in the multilevel hierarchy, the main memory being at a lowest hierarchical level, each of the cache levels having a cache memory;
identifying a cache level code associated with a data request issued by the central processor, the cache level code indicating a hierarchical level in the multilevel hierarchy, the data request having a specified address;
and
determining from the cache level code which cache memories can be written to with data associated with the specified address and which cache memories cannot be written to with the data associated with the specified address.

1 more element

Dependencies are inferred from the claim text.

Memory system and method for selective multi-level caching using a cache level code

Life of this patent

Memory system and method for selective multi-level caching using a cache level code

Life of this patent

Abstract

Claims26