Method and apparatus for binding instructions to dispatch ports of a reservation station
AssigneeIntel Corporation
InventorsJames S. Griffith, Shantanu R. Gupta, Glenn J. Hinton
Life of this patent
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Abstract
A method and apparatus for binding instructions to dispatch ports in a reservation station includes a counter mechanism and a port identifier. The counter mechanism maintains a count of instructions which are pending dispatch from at least one of the dispatch ports. The port identifier receives an instruction and identifies to which of the dispatch ports the instruction is to be bound, based on the count of instructions maintained by the counter mechanism.
Claims22
An apparatus for identifying a first dispatch port of a reservation station from which an instruction is to be dispatched, wherein the instruction could be dispatched from a plurality of dispatch ports of the reservation station, the apparatus comprising:
- a counter mechanism to maintain a first count of instructions which are pending dispatch from the first dispatch port of the plurality of dispatch ports;
- and
- a port identifier, coupled to the counter mechanism, to identify the first dispatch port based on the first count of instructions.
An apparatus for binding an instruction to one of a plurality of dispatch ports in a reservation station, the apparatus comprising:
- an allocator for receiving the instruction and, upon receipt of the instruction, for identifying a first dispatch port to the reservation station, wherein the identifying binds the instruction to the first dispatch port, and wherein the allocator includes a port identifier for identifying the first dispatch port, wherein the port identifier identifies the first dispatch port based on both the instruction and a count of instructions in the reservation station which are tagged for dispatch from the first dispatch port;
- and
- wherein the reservation station is coupled to the allocator and wherein the reservation station is for buffering the instruction and also for dispatching the instruction to the first dispatch port.
An apparatus comprising:
- a reservation station for buffering an instruction and also for dispatching the instruction from a first dispatch port of a plurality of dispatch ports, wherein the instruction could be dispatched from any one of the plurality of dispatch ports;
- and
- an allocator for receiving the instruction from an instruction decode unit, wherein the allocator is coupled to the reservation station, and wherein the allocator includes,
- a port identifier for identifying to the reservation station the first dispatch port based on a number of instructions pending dispatch from the first dispatch port.
An apparatus for tagging an instruction for dispatch from one of a plurality of dispatch ports, the apparatus comprising:
- a reservation station for buffering a plurality of instructions and also for dispatching the plurality of instructions from the plurality of dispatch ports;
- and
- an allocator for receiving the plurality of instructions concurrently from an instruction decode unit, wherein the allocator is coupled to the reservation station, and wherein the allocator includes,
- a plurality of port identifiers corresponding to the plurality of instructions, wherein the plurality of port identifiers, in response to the receipt of the plurality of instructions, identifies to the reservation station a set of the plurality of dispatch ports from which the plurality of instructions is to be dispatched based on a number of instructions which are pending dispatch over the set of the plurality of dispatch ports.
A computer system comprising:
- a bus;
- a memory device which stores an instruction, wherein the memory device is coupled to the bus;
- and
- one or more processors coupled to the bus, wherein each of the one or more processors includes,
- a plurality of execution units;
- a reservation station for buffering a plurality of instructions, including the instruction, prior to dispatch to the plurality of execution units and also for dispatching the instruction to an execution unit of the plurality of execution units from a first dispatch port of a plurality of dispatch ports, and
- an allocator for receiving the instruction from the memory device and, upon receipt of the instruction, for identifying the first dispatch port to the reservation station, wherein the allocator includes a port identifier for identifying the first dispatch port, wherein the port identifier is for identifying the first dispatch port based on both the instruction and a count of instructions in the reservation station which are pending dispatch from the first dispatch port.
A method for identifying a first dispatch port of a reservation station from which an instruction is to be dispatched, wherein the instruction could be dispatched from a plurality of dispatch ports of the reservation station, the method comprising the steps of:
- (a) receiving the instruction;
- (b) determining a number of instructions which are pending dispatch from at least one of the plurality of dispatch ports;
- and
- (c) identifying the first dispatch port based on the number of instructions which are pending dispatch from the at least one of the plurality of dispatch ports.
An apparatus for identifying a first dispatch port of a plurality of dispatch ports of a reservation station from which an instruction is to be dispatched, wherein the instruction could be dispatched from any one of the plurality of dispatch ports, the apparatus comprising:
- means for maintaining a first count of instructions which are pending dispatch from the first dispatch port and a second count of instructions which are pending dispatch from a second dispatch port of the plurality of dispatch ports;
- and
- means, coupled to the means for maintaining, for identifying the first dispatch port based on both the first count of instructions and the second count of instructions.
Dependencies are inferred from the claim text.