Reconfigurable torus network having switches between all adjacent processor elements for statically or dynamically splitting the network into a plurality of subsystems

A reconfigurable torus network system for use in a parallel computer comprising:

• a system manager outputting first and second control signals;
• first, second and third processor element subsets, each comprising at least one processor element, and each comprising respective input and output terminals;
• a first switch connected to the input terminal and the output terminal of said first processor element subset, and connected to the output terminal of said second processor element subset;
• a second switch connected to said first switch, connected to the input terminal of said second processor element subset, and connected to the input terminal and the output terminal of said third processor element subset;
• and
• switch control means for controlling the first and second switches to connect the output terminal of said first processor element subset to the input terminal of said second processor element subset through said first and second switches in response to the first control signal, and for controlling the first switch to connect the output terminal of the first processor element subset to the input terminal of the first processor element subset through the first switch in response to the second control signal.

A reconfigurable torus network system for a parallel computer comprising:

• first and second processor element subsets, each comprising at least one processor element, and each comprising respective input and output terminals;
• a first switch electrically connected to the input and the output terminals of said first processor element subset, and to the output terminal of said second processor element subset;
• a second switch electrically connected to said first switch and the input terminal of said second processor element subset;
• and
• a third processor element subset, comprising at least one processor element and respective input and output terminals, wherein the input and output terminals are connected to said second switch;
• wherein data from said first processor element subset is transferred from the output terminal of said first processor element subset to said first switch, to said second switch, to the input terminal of said third processor element subset, to the output terminal of said third processor element subset, to said second switch and then to said second processor element subset.

A reconfigurable N dimensional torus network system including a plurality of one dimensional torus networks for use in a parallel computer, each one dimensional torus network comprising:

• a plurality of processors each having respective input and output terminals;
• a first set of switches disposed between first and second adjacent processors;
• a second set of switches disposed on first and second ends of the torus network;
• and
• interleave connection means for setting one of said first set of switches to electrically connect an output terminal of said first processor to an input terminal of a third processor which is non-adjacent to said first processor such that data from said first processor element is directly transferred to said third processor, and for setting one of said second set of switches to electrically connect an input terminal of the second processor element to an output of a fourth processor element existing on an end of said torus network through a switch of said first set of switches.

A reconfigurable N dimensional torus network system including a plurality of one dimensional torus networks for use in a parallel computer, each one dimensional torus network comprising:

• a plurality of processors each having respective input and output terminals;
• a first set of switches disposed between first and second adjacent processors;
• a second set of switches disposed on first and second ends of the torus network;
• and
• interleave connection means for setting one of said first set of switches to electrically connect an output terminal of said first processor to an input terminal of a third processor which is non-adjacent to said first processor such that data from said first processor is directly transferred to said third non-adjacent processor and for setting one of said second set of switches to electrically connect an output terminal of the second processor to an input of a fourth processor existing on an end of said torus network through a switch of said first set of switches.

A reconfigurable torus network system for use in a parallel computer comprising:

• first, second and third adjacent processor element subsets, each comprising at least one processor element, and having respective input and output terminals;
• a first switch connected to the output terminal of said first processor element subset;
• a second switch connected to the input terminal of said third processor element subset and said first switch;
• and
• interleave connection means for setting said first and second switches to electrically connect the output terminal of said first processor element subset to the input terminal of said third processor element subset such that data from said first processor element subset is directly transferred to said third processor element subset and for setting said second switches to electrically connect the output terminal of said third processor element subset to the input terminal of said second processor element subset to thereby transfer data from said first processor element subset to said second processor element subset through said third processor element subset.