Data processing system
AssigneeKabushiki Kaisha Toshiba
InventorMiho Koga
Life of this patent
Estimating the term…
Abstract
A data processing system has a processor, a RAM, an arithmetic unit, an address bus, a data bus, a state unit, and a bus controller. The state unit checks a front half and a rear half of a bus cycle of the processor, and generates a control signal indicating the front half and the rear half of the bus cycle. The bus controller receives the control signal, and based on the received control signal, indicates to the arithmetic unit receiving data transmitted from the RAM during the front half of the bus cycle, and to the processor receiving data transmitted from the arithmetic unit during the rear half of the bus cycle through the data bus.
Claims11
A data processing system comprising:
- processor means;
- a first device;
- a second device;
- an address bus and a data bus through which the processor, the first device, and the second device are connected;
- state means for checking a front half and a rear half of a bus cycle of the processor means, and generating a control signal indicating the front half and the rear half of the bus cycle;
- and
- control means for receiving the control signal from the state means and address data through the address bus, and based on the received address data for outputting a signal indicative of the first device to transmit data and indicative of the second device to receive the data transmitted from the first device during the front half of the bus cycle, and for outputting a signal indicative of the second device to transmit data to the processor during the rear half of the bus cycle.
A data processing system comprising:
- processor means;
- first to n-th devices;
- an address bus and a data bus through which the processor means and the first to n-th devices are connected;
- state means for checking a front half and a rear half of a bus cycle of the processor means, and generating a control signal indicating the front half and the rear half of the bus cycle;
- and
- control means for receiving address data through the address bus and transmitting a device control signal to the first to n-th devices to be accessed, and
- when the bus cycle executed by the processor means is a bus cycle for accessing one of the n-th devices indicated by the device control signal transmitted from the control means and the control signal from the state means indicates the front half of the bus cycle, the control means controls one of the first to n-th devices which are not selected by the device control means to transmit data therein and controls the one of the n-th devices indicated by the device control signal to receive the data through the data bus, and
- when the bus cycle executed by the processor means is a bus cycle for accessing one of the n-th devices indicated by the device control signal transmitted from the control means and the control signal from the state means indicates the rear half of the bus cycle, the control means controls the one of the n-th devices selected by the address control signal to transmit data to the data bus and controls the processor means to receive the data through the data bus.
A data processing system comprising:
- a processor;
- an arithmetic unit;
- a random access memory;
- a system bus through which said processor, said arithmetic unit and said randam access memory are interconnected in order to carry out data exchange thereamong;
- a bus controller connected to said processor, said arithmetic unit and said randam access memory for controlling read/write operations thereof via said system bus;
- and
- a state generation logic unit connected to said bus controller and said system bus for generating a state signal indicating a front half or a rear half of a bus cycle,
- wherein said processor initiates the bus cycle by outputting to said bus controller through said system bus an information signal indicative of an operation to be performed and a necessary address, and
- wherein said bus controller controls data exchange between said arithmetic unit and said randam access memory in accordance with said information signal and said state signal generated by said state generation logic unit.
Dependencies are inferred from the claim text.