US 5,689,657 AGranted

Apparatus and methods for bus arbitration in a multimaster system

AssigneeDeutsche ITT Industries GmbH

InventorsHans-Jurgen Desor, Soenke Mehrgardt

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Abstract

A bus arbitration method for a multimaster system comprising a plurality of masters sharing a global data bus and a plurality of bus arbiters sharing a global identification bus. Each active bus arbiter applies to the identification bus a bus request signal containing a k-bit-wide identification word representative of the priority of the master associated with the bus arbiter. In each prioritization step of the bus grant cycle, a logic level is produced on the identification bus by logically combining bits of equal significance. This logic level is then compared with the corresponding bits of the applied identification words. The k bits of the identification words of the bus arbiters are placed on the identification bus on a time-graded basis; in each prioritization step of the bus grant cycle, only those bits of the identification words are placed on the identification bus which are of equal significance, and in each prioritization step of the bus grant cycle, those bus arbiters whose identification word bit in the prioritization step does not match the logic level of the identification bus are eliminated from the bus arbitration of the bus gram cycle.

Claims19

Dependent claims

A bus arbitration apparatus for use in a video system comprising:

a data bus;
an identification bus, said identification bus including a plurality of logic lines;
a plurality of video sources, each of said video sources corresponding to a plurality of pixel signals representative of observer-visible pixels, each of said video sources having means for selecting a particular pixel signal from said plurality of pixel signals for transmission to said data bus, coupled to said data bus and each having a predetermined priority for accessing said data bus, said predetermined priority of each of said video sources determined in accordance with an identification word associated with each of said video sources and wherein each said identification word includes a plurality of bits;
means for forming a logic level on said identification bus by logically combining equally significant bits of each of said identification words;
means for performing a plurality of overlapping bus grant cycles, wherein each of said plurality of bus grant cycles determines priority among said plurality of said video sources by successively comparing, during a system dock time period, said equally significant bits of each of said identification words with said logic level on each of said logic lines on said identification bus, to eliminate each of said plurality of video sources having an associated identification word containing a bit that does not correspond to said logic level, wherein each of said successive comparisons occurs during each successive system clock time period, wherein each of said bus grant cycles includes multiple system clock time periods;
and
means for granting access to said data bus to one of said plurality of video sources that is not eliminated during each of said bus grant cycles.

4 more elements

Dependencies are inferred from the claim text.