US 5,689,653 AGranted

Vector memory operations

AssigneeHewlett-Packard Company

InventorsAlan H. Karp, Frederic C. Amerson, Dennis Brzezinski, Rajiv Gupta, William S. Worley, Jr.

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Abstract

The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.

Claims20

Dependent claims

A computer system comprising:

a memory hierarchy including a cache memory and a main memory;
a register file comprising a plurality of registers;
a vector buffer for storing a load vector comprising a plurality of data elements obtained from the memory hierarchy and for storing a store vector comprising a plurality data elements for transfer to the memory hierarchy;
a vector prefetch unit in communication with the memory hierarchy, the register file, and the vector buffer and operative to transfer the data elements of the load vector and the data elements of the store vector between the memory hierarchy and the vector buffer, and between the vector buffer and the register file;
and
an instruction unit in communication with the memory hierarchy and the vector prefetch unit, the instruction unit being operative to read the coded instructions from the memory hierarchy,
the instruction unit being operative, in response to a vector request instruction specifying the data elements of the load vector and the data elements of the store vector, to cause the vector prefetch unit to transfer the data elements of the load and store vectors between the memory hierarchy and to the vector buffer, and
the instruction unit being operative, in response to a vector element operation instruction, to cause the vector prefetch unit to transfer a next one of the data elements of the load vector in the vector buffer from the vector buffer to the register file and to transfer a data element contained in the register file from the register file to the vector buffer to provide a next one of the data elements of the store vector while transferring the next one of the data elements from the vector buffer to the register file.

5 more elements

A computer system comprising:

a memory hierarchy comprising a cache memory and a main memory for storing a set of coded instructions of a program;
a vector buffer for storing a load vector comprising a plurality of data elements of the program obtained from the memory hierarchy and for storing a store vector comprising a plurality of data elements of the program for transfer to the memory hierarchy;
a register file comprising a plurality of processor registers for use in processor operations;
vector buffer control registers for storing data identifying the data elements of the load vector and the data elements of the store vector;
a vector buffer controller in communication with the vector buffer, the memory hierarchy, the register file, and the vector buffer control registers for controlling transfer of the data elements of the load and store vectors specified in the vector buffer control registers between the memory hierarchy and the vector buffer, and for controlling transfer of the data elements of the load and store vectors consecutively between the vector buffer and the register file;
and
a processor in communication with the memory hierarchy and the vector buffer controller for retrieving the coded instructions from the memory hierarchy and executing operations corresponding to the coded instructions, the processor being responsive to a vector request instruction specifying the data elements of the load and store vectors to load the vector buffer control registers with the data identifying the data elements of the load and store vectors and to initiate transfer of the data elements of the load and store vectors by the vector buffer controller between the memory hierarchy and the vector buffer, the processor being responsive to a vector element operation instruction to initiate transfer of a next one of the data elements of the load vector in the vector buffer from the vector buffer to the register file and to initiate transfer of a data element contained in the register file from the register file to the vector buffer to provide a next one of the data elements in the store vector such that the next one of the data elements of the load vector is transferred to the register file while the data element is transferred to the vector buffer.

4 more elements

A method for performing vector memory operations in a computer system, comprising the steps of:

in response to a vector request instruction specifying an address, a length and a stride for each of a first and a second set of data elements, obtaining the first set of data elements from a memory hierarchy and buffering the first set of data elements obtained from the memory hierarchy as a load vector and transferring the second set of data elements being buffered as a store vector to the memory hierarchy;
in response to each of a plurality of vector element operation instructions specifying a register in a processor register file, transferring a next one of the first set of data elements of the load vector being buffered to the processor register file and transferring a data element out of the processor register file while the next one of the first set of data elements of the load vector being buffered is transferred to the processor register file and buffering the data element from the processor register file as a next one of the second set of data elements of the store vector.

Dependencies are inferred from the claim text.