US 5,689,647 AGranted

Parallel computing system with processing element number setting mode and shortest route determination with matrix size information

AssigneeSanyo Electric Co., Ltd.

InventorHiroki Miura

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Abstract

A parallel computer system includes a plurality of processing elements each including a network control unit and a data processing unit. The network control unit of each processing element includes a north, east, west and south ports to each of which a row and column communication lines are connected so as to construct a torus mesh network. A specific mode flag which is set by a reset signal from a host computer coupled to the network and a number register are formed in the data processing unit. If a packet is sent to the network from the host computer when the specific mode flag is set, in the processing element which received the packet, the processing element number included in the packet is set in the number register and the specific mode flag is reset so that the processing element can be identified by that processing element number in a normal mode. In the normal mode, the packet is inputted to the data processing unit when the processing element number of the packet is coincident with its own processing element number. If not coincident, the packet is outputted to a port determined by a predetermined algorithm so that the packet can be transferred to an addressed processing element on the network with the shortest distance.

Claims44

Dependent claims

A parallel computer system comprising:

a plurality of processing elements, each of said processing elements including
a network control unit having a plurality of individual communication ports,
a data processing unit, and
a mode flag capable of being selectively set for operating the processing element in a first number setting mode or a second normal operation mode,
each said network control unit receiving data sets that each contain a processing element identifying number and performing a transfer control of the received data sets;
a plurality of individual communication lines for coupling the plurality of individual communication ports of said network control units of said plurality of processing elements into a network;
sending means for sequentially sending the data sets onto said network, said sending means sending each data set with a different processing element identifying number while any of said processing elements are in said first number setting mode;
holding means in each of said plurality of processing elements for holding a respective processing element identifying number corresponding to each said processing element as received in a data set from said sending unit;
and
number setting means in each of said plurality of processing elements for setting said processing element identifying number, wherein
each of the network control units, (i) while its respective processing element is in said first number setting mode, transfers each received data set to its own processing element irrespective of the processing element identifying number contained in the received data set arriving at any one of said plurality of communication ports of a said processing element, (ii) while said own processing element is in said second normal mode transfers the received data set to said own processing element only when the processing element identifying number contained in the data set is equal to the processing element identifying number held by said own processing element, and (iii) while a said processing element is in said second normal mode and at a time when the processing element identifying number contained in the received data set is not equal to the respective processing element identifying number held by its own processing element, transfers the data set to a selected one of said plurality of communication ports of the processing element, and
means in each of said processing elements for setting the mode flag in said normal operation mode when said processing element identifying number is held by said holding means.

9 more elements

A parallel computer system comprising:

a plurality of processing elements, each of said plurality of processing elements including
means for storing a number identifying the corresponding processing element,
means for holding network size data representative of the size of the network in which the plurality of processing elements are located,
a network control unit having ports, N, E, S, W, each said network control unit receiving data sets addressed to a respective destination processing element in terms of a processing element identifying number of an x (row) direction and a y (column) direction, and
a data processing unit including means for outputting and receiving data to and from said ports;
communication lines coupling the E and W ports of the respective network control units of n processing elements in the x direction and the N and S ports of m processing elements in the y direction to construct a network, the size of said network being represented by said network size data in a received data set;
and
each said processing element including routing means for determining, on the basis of the addressed destination processing element identifying number and said network size data in a received data set, a port from which data is to be outputted from said data processing unit and transferred to a given port of an addressed destination processing element over the shortest routing distance on the basis of the difference dx-x, dy-y, between the destination processing element identifying number dx, dy and identifying number x, y held in its number holding means to determine the port from which data is to be output so that the data can be transferred to the destination processing element over the shortest distance on the basis of the difference dx-x, dy-y, and the network size, the outputted data of a processing element outputting such data including the processing element identifying number of the addressed destination processing element.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/551,694Filed 1 Nov 1995 · continuation
Priority: JP 1-6309114 Mar 1989
Granted: 18 Nov 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 15/8092
Vector processors: array of vector units
G06F 9/4494
Execution paradigms, e.g. implementations of programming paradigms: data driven
G06F 15/17337
Using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake: direct connection machines, e.g. completely connected computers,…
G06F 15/8023
Single instruction multiple data [SIMD] multiprocessors: two dimensional arrays, e.g. mesh, torus