Microprocessor memory test circuit and method
AssigneeSGS-Thomson Microelectronics S.A.
InventorGianluca Petrosino
Life of this patent
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Abstract
A circuit and method for testing on-chip memory for a microprocessor or a microcomputer is disclosed. The memory test circuit includes an input register, an output register, an adder, and a sequencer to control the test process. The process includes receiving a simple communication protocol from the control unit to start the test, running a common memory test such as a checker board, AAAAh, 5555h and the like, and then storing the test results in an output register. The test circuit can include a bi-directional RESET signal means for disabling the system while the microprocessor or microcomputer runs its memory test.
Claims20
A method for testing a plurality of volatile memory cells on a microprocessor for use in an electronic system comprising the steps of:
- holding a reset line down after a power-up of said microprocessor to disable the electronic system other than the microprocessor until said plurality of volatile memory cells have been tested;
- testing said plurality of volatile memory cells;
- replacing a failed memory cell with a redundant memory cell, and,
- releasing the reset line after said plurality of volatile memory cells have been tested.
A microprocessor for use in an electronic system comprising:
- volatile memory having an address bus and a data bus;
- a test bus in addition to the address bus and data bus of said volatile memory;
- an on-chip memory test circuit coupled to said test bus;
- and
- means for disabling the electronic system other than the microprocessor until said volatile memory had been tested.
A microcontroller for use in an electronic system comprising:
- volatile memory having an address bus and a data bus;
- a test bus in addition to the address bus and data bus of said volatile memory;
- an on-chip memory test circuit coupled to said test bus;
- and
- means for disabling the electronic system other then microcontroller until said volatile memory has been tested.
Dependencies are inferred from the claim text.