Three purpose shadow register attached to the output of storage devices

A multi-purpose shadow register apparatus in a computer system, said computer system having a central processing unit, a memory, a memory output select circuit, and a memory output bus which provides memory output data from the memory to the memory output select circuit, said multi-purpose shadow register apparatus comprising:

• a shadow register in parallel with the memory output select circuit and connected to receive memory output data from the memory output bus and functional logic block data from a functional logic block data bus and comprising bus selection means for selecting input from either the memory output bus or the functional logic block data bus, and said shadow register being responsive to an output enable signal to provide shadow register output data on a shadow register output bus;
• and
• a shadow register functional logic block comprising a plurality of functional blocks, each functional block utilizing the shadow register in a mutually time-exclusive manner, said shadow register functional logic block producing functional logic block data on said functional logic block data bus, wherein the shadow register functional logic block includes functional blocks comprising a signature analyzer, a parity checker, and a diagnostics read circuit;
• said signature analyzer connected to receive the memory output data from the memory output bus for performing a signature analysis function on the memory output data and producing signature data as the functional logic block data on the functional logic block data bus;
• said parity checker connected to receive the memory output data from the memory output bus for detecting a parity error in said memory output data and providing a parity error indicator from which the memory output data is caused to be trapped in the shadow register and provided as shadow register output data on the shadow register output bus;
• said bus selection means of the shadow register configured to select as input the functional logic block data from the functional logic block data bus when the signature analyzer is in operation and configured to select as input the memory output data from the memory output bus when the parity checker or the diagnostics read circuit is in operation.