Refined timing recovery circuit

Abstract

Briefly, in accordance with one embodiment of the invention, a refined timing recovery circuit for retiming a recovered data signal comprises a data pulse edge detector. The recovered data signal is derived from a received data pulse. The data pulse edge detector is adapted to be coupled to an oversampling clock. The data pulse edge detector is further adapted to sense the next clock pulse edge having the closest temporal proximity after a selected received data pulse edge. In accordance with another embodiment, an integrated circuit comprises: a timing recovery system for retiming a recovered data signal derived from a received data pulse, the timing recovery system comprising a refined timing recovery circuit. The refined timing recovery circuit includes a data pulse edge detector. The data pulse edge detector is adapted to be coupled to an oversampling clock having a mutually timed series of clock pulses at a substantially predetermined frequency and is further adapted to sense the next clock pulse edge having closest temporal proximity after a selected received data pulse edge. In accordance with yet another embodiment, a method of reducing the phase quantization error of a recovered data signal derived from a received data pulse by sampling with digital clock pulses at a first substantially predetermined frequency comprising the steps of: sampling the received data pulse with digital clock pulses at a second substantially predetermined frequency so as to sense the next clock pulse edge of the digital clock pulses in closest temporal proximity after a selected edge of the received data pulse, the second substantially predetermined frequency being approximately M times the first substantially predetermined frequency; and retiming the recovered data signal substantially in accordance with the sensed next clock pulse edge.

Dependencies are inferred from the claim text.