PN code synchronizing method and transmitter and receiver in spread spectrum communication systems
AssigneeNEC Corporation
InventorsTetsuya Takaki, Kenji Ishida
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Abstract
A PN code synchronizing method in spread spectrum communication systems of the present invention calculates a matrix H based on tap locations of a PN code generating shift register, also calculates an internal status of the PN code generating shift register at a time t+M by multiplying an internal status of the PN code generating shift register at a time t by M-th power of the matrix H, and transmits the internal status of the PN code generating shift register at a time t+M to reception side through a synchronous channel. in reception side, a PN code generating shift register therein is set based on the internal status of the PN code generating shift register at a time t+M.
Claims19
A PN code synchronizing method in spread spectrum communication systems using a plurality of traffic channels and at least one synchronous channel, comprising a step of calculating a value by multiplying an internal status of a PN code generating shift register at a time t by M-th power of a matrix H (H.sup.M) that is preset in advance and transmitting said value to a receiver through said synchronous channel.
A PN code synchronizing method in spread spectrum communication systems using a plurality of traffic channels and at least one synchronous channel, comprising:
- (1) step of calculating a matrix H based on tap locations of a PN code generating shift register;
- (2) step of calculating an internal status of said PN code generating shift register at a time t+M by multiplying an internal status of a PN code generating shift register at a time t by M-th power of said matrix H (H.sup.M), and transmitting said internal status of said PN code generating shift register at the time t+M through said synchronous channel;
- and
- (3) step of receiving said internal status of said PN code generating shift register at the time t+M transmitted through said synchronous channel, setting said internal status of said PN code generating shift register at the time t+M in a shift register of said receiver.
A spread spectrum transmitter comprising:
- a shift register for generating a PN code;
- and
- a calculating means for calculating an internal digital value of the shift register after the elapse of time "M" using a matrix H.sup.M, wherein the term "M" represents the time from when a receiver receives a synchronization channel to when the receiver receives a signal on the communication channel.
A spread spectrum transmitter comprising:
- a shift register for generating a PN code;
- a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t,
- said calculating means comprising:
- a first storing means for storing said internal status of shift register at the time t;
- a second storing means for storing M-th power of a matrix H (H.sup.M) derived from tap locations of said shift register;
- a multiplying means for multiplying the contents stored in said first storing means and the contents of said second storing means;
- and
- a third storing means for storing a calculation result of said multiplying means.
A spread spectrum transmitter comprising:
- a shift register for generating a PN code;
- a calculating means for calculating an internal status of shift register at a time after a predetermined time interval M from a time t;
- and
- further comprising a transmitting means for transmitting an internal status of shift register at a time after the time interval M from the time t.
A spread spectrum transmitter comprising:
- a shift register for generating a PN code;
- a 1 bit.times.n word memory for storing an internal status of shift register at a time t, where length of said shift register is n;
- an n bit.times.n word memory for storing M-th power of a matrix H (H.sup.M) derived from tap locations of said shift register;
- an n bit.times.1 word memory for storing an internal status of shift register at a time t+M;
- a deciding means for fetching the contents of said 1 bit.times.n word memory from address 1 to address n one by one, and detecting an address storing 1;
- a counter for counting a number of operations of said deciding means;
- and
- an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit.times.n word memory which is corresponding to the detected address storing 1 of said 1 bit.times.n word memory and the contents of said n bit.times.1 word memory and storing this calculation result into said n bit.times.1 word memory until the counted number of said counter becomes n.
A spread spectrum receiver comprising:
- a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code;
- and
- a calculating means for calculating an internal status of shift register at a time s+N based on said internal status of shift register at the time s.
A spread spectrum receiver comprising:
- a shift register being set in an internal status of shift register at the time s that has been transmitted, for generating a PN code;
- a 1 bit.times.n word memory for storing an internal status of shift register at a time s, where length of said shift register is n;
- an n bit.times.n word memory for storing N-th power of a matrix H derived from tap locations of said shift register;
- an n bit.times.1 word memory for storing an internal status of shift register at a time s+N;
- a deciding means for fetching the contents of said 1 bit.times.n word memory from address 1 to address n one by one, and detecting an address storing 1;
- a counter for counting a number of operations of said deciding means;
- and
- an exclusive-OR calculating means for calculating, when having detected an address storing 1, exclusive-OR of the contents of an address of said n bit.times.n word memory which is corresponding to the detected address storing 1 of said 1 bit.times.n word memory and the contents of said n bit.times.1 word memory and storing this calculation result into said n bit.times.1 word memory until the counted number by said counter becomes n.
Dependencies are inferred from the claim text.