Reset circuit for a programmable logic device
AssigneeXilinx, Inc.
InventorsRonald J. Mack, Derek R. Curd, Sholeh Diba, Napoleon W. Lee, Kameswara K. Rao, Mihai G. Statovici
Life of this patent
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Abstract
A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.
Claims10
An integrated circuit comprising:
- a JTAG instruction port;
- JTAG circuitry having a first input node connected to the instruction port and a second input node;
- and
- programmable memory including a programmable JTAG-disable-bit storage location connected to the second input node of the JTAG circuitry.
A method of testing an integrated circuit, wherein the integrated circuit includes functional circuitry and JTAG circuitry, the method comprising the steps of:
- testing the JTAG circuitry;
- testing the functional circuitry;
- and
- if the steps of testing the JTAG circuitry and the functional circuitry indicate that the JTAG circuitry is not operational and the functional circuitry is operational, disabling the JTAG circuitry.
An integrated circuit comprising:
- JTAG circuitry;
- a programmable JTAG-disable-bit storage location for selectively disabling the JTAG circuitry;
- means for testing the JTAG circuitry to determine whether the JTAG circuitry is defective;
- and
- means for programming the JTAG-disable-bit storage location if the means for testing detects a defect, thereby disabling the JTAG circuitry.
A structure for testing JTAG and logic circuits, the structure comprising:
- a logic circuit structure;
- a JTAG test structure;
- means for resetting the logic circuit structure in response to a logic reset signal and a JTAG reset signal;
- and
- means for disabling the JTAG test structure in response to the JTAG reset signal.
Dependencies are inferred from the claim text.