Method and apparatus for testing the address system of a memory system
AssigneeInternational Business Machines Corporation
InventorToshiharu Saitoh
Life of this patent
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Abstract
A method and apparatus for testing or verifying proper operation of an address system of a memory system are provided. The address system includes a write unit for driving write word lines, based on a write address, and a read unit for driving read word lines, based on a read address. A common address is applied to the write unit and read unit, and the outputs thereof are compared for equivalency, using a verification circuit. Proper operation of the address system is indicated by the verification circuit if the outputs of the write and read units are equivalent, and improper operation is indicated if the outputs are not equivalent.
Claims48
A memory system, comprising:
- an array of memory cells operable with a plurality of write word lines and a plurality of read word lines;
- an address system coupled to the plurality of write word lines and the plurality of read word lines, the address system including:
- a write address unit for producing, from a write address, write signals on the plurality of write word lines, and
- a read address unit for producing, from a read address, read signals on the plurality of read word lines;
- and
- a verification circuit coupled to receive the write signals and the read signals, such that upon application of the write and read addresses to the write address unit and the read address unit of the address system respectively, the write signals and the read signals produced thereby are processed by the verification circuit to verify proper operation of the address system.
A method for verifying proper operation of an address system of a memory array having a plurality of memory cells arranged therein, the plurality of memory cells operated using a plurality of write word lines and a plurality of read word lines, the address system producing write signals on the plurality of write word lines from a write address and producing read signals on the plurality of read word lines from a read address, the method comprising:
- applying a common test address, as the read address and the write address, to the address system;
- and
- comparing the write signals produced by the address system from the common test address to the read signals produced by the address system from the common test address to verify proper operation of the address system.
A method for verifying proper operation of an address system of a memory array, comprising:
- comparing first word line outputs of a first unit of said address system to second word line outputs of a second unit of said address system upon application of a common address to both the first unit and the second unit.
A system for verifying proper operation of an address system of a memory array having a plurality of memory cells arranged therein, the plurality of memory cells operated using a plurality of write word lines and a plurality of read word lines, the address system producing write signals on the plurality of write word lines from a write address and producing read signals on the plurality of read word lines from a read address, the system comprising:
- means for applying a common test address, as the read address and the write address, to the address system;
- and
- means for comparing the write signals produced by the address system from the common test address to the read signals produced by the address system from the common test address to verify proper operation of the address system.
A system for verifying proper operation of an address system of a memory array, comprising:
- means for comparing first word line outputs of a first unit of said address system to second word line outputs of a second unit of said address system upon application of a common address to both the first unit and the second unit.
A memory system, comprising:
- an array of memory cells operable with a plurality of first word lines and a plurality of second word lines;
- an address system coupled to the plurality of first word lines and the plurality of second word lines, the address system including:
- a first address unit for producing, from a first address, first signals on the plurality of first word lines, and
- a second address unit for producing, from a second address, second signals on the plurality of second word lines;
- and
- a verification circuit coupled to receive the first signals and the second signals, such that upon application of the first and second addresses to the first address unit and the second address unit of the address system respectively, the first signals and the second signals produced thereby are processed by the verification circuit to verify operation of the address system.
Dependencies are inferred from the claim text.