Multi-bank synchronous memory system with cascade-type memory cell structure

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines;
• a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells;
• a plurality of second memory cells corresponding to the plurality of first memory cells;
• a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells into each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal;
• and
• wherein the sense amplifier comprises a first type MOS transistor pair connected in series and a second type MOS transistor pair connected in series, the first type MOS transistor pair and the second type MOS transistor pair are connected to a bit line pair in parallel, the bit line pair having first and second bit lines, gates of two of the transistors of opposite type being connected to the first bit line and gates of the other two transistors of opposite type being connected to the second bit line.

A synchronous memory system with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell is performed in synchronization with a first clock signal supplied from an external device, the synchronous memory system comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of first memory cells having a cascade-type configuration connected to the plurality of word lines, the plurality of first memory cells forming a first memory cell group in a plurality of first memory cell group in a memory cell array, the first memory cell group being connected to one of the plurality of bit lines;
• a sense amplifier for sensing data to be written into the plurality of first memory cells or for sensing data read out from the plurality of first memory cells;
• a plurality of second memory cells corresponding to the plurality of first memory cells;
• a decoder for receiving an address signal for a target memory cell to be accessed in the plurality of first memory cells in order to perform a sense operation based on the first clock signal, and controlling a transmission of data stored in each of the plurality of first memory cells in to each of the plurality of second memory cells in synchronism with a second clock signal generated by using the first clock signal;
• and
• wherein the number of the plurality of first memory cells connected in the cascade-type configuration per first memory cell group is four first memory cells.

A multi-bank synchronous memory system with a multi-bank structure comprising:

• a plurality of synchronous memory systems with a cascade-type memory cell structure in which receiving of an address for a memory cell to be accessed and readout of data stored from the memory cell being performed in synchronization with a first clock signal supplied externally, and the plurality of synchronous memory cell systems being divided into a plurality of banks in a multi-bank structure, data in the memory cell in each bank being sensed independently, and
• each of the plurality of synchronous memory systems comprising:
• a plurality of word lines;
• a plurality of bit lines;
• a plurality of first memory cells having a cascade-type configuration connected to the plurality of word selection lines, the plurality of first memory cells forming a memory cell group in a plurality of memory cell groups in a memory cell array, the memory cell group being connected to one of the plurality of bit lines;
• a plurality of transfer gates provided to each of the plurality of the bit lines to connect each memory cell group to each of the plurality of the bit lines;
• a sense amplifier connected to each of the plurality of bit lines for storing data to be written into each of the plurality of first memory cells or for storing data to be read out from each of the plurality of first memory cells;
• an equalizer provided for the sense amplifier for equalizing a voltage potential of each of the plurality of bit lines;
• a plurality of second memory cells located between the plurality of first memory cells and the sense amplifier, the plurality of second memory cells provided for the plurality of first memory cells;
• a selector for receiving an address of a target memory cell to be accessed in the plurality of first memory cells according to the first clock signal,
• selecting each of the plurality of first memory cells while saving data of the selected each of the plurality of first memory cells to the plurality of second memory cells in synchronism with the first clock signal and counting a number of the selected each of the plurality of first memory cells,
• generating a sense operation halt control signal when the target memory cell being selected and whose data being stored to the sense amplifier, and transmitting the sense operation halt control signal externally;
• and
• a decoder for receiving the address of the target memory cell and generates access control signals for controlling operations of the plurality of first memory cells, the plurality of transfer gates, the sense amplifier, the equalizer, and the plurality of second memory cells, and transmits the address control signals to the plurality of word lines, the plurality of transfer gates, the plurality of second memory cells, and the sense amplifier,
• wherein when a memory cell in the plurality of first memory cells in another memory cell group connected is a target memory cell to be accessed in series, a sense operation for the first memory cells including the target memory cell in another memory cell group is executed after the data items temporarily have been saved into the plurality of second memory cells are restored into corresponding the plurality of first memory cells including the preceding target memory cell.