Semiconductor memory device and method for accessing a memory in the same
AssigneeSharp Kabushiki Kaisha
InventorKouji Inoue
Life of this patent
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AssigneeSharp Kabushiki Kaisha
InventorKouji Inoue
Estimating the term…
A semiconductor memory device includes a plurality of memory cells arranged in a matrix, each of which has a gate electrode, a first electrode and a second electrode. The semiconductor memory device includes a plurality of word lines, at least one of which is connected to the gate electrode of one of the plurality of memory cells; a plurality of bit lines, at least one of which is connected to the first electrode of one of the plurality of memory cells and a plurality of virtual ground lines, at least one of which is connected to the second electrode of one of the plurality of memory cells. The semiconductor memory device also includes a determination circuit for generating a determination signal based on an address signal, and a precharge and access circuit for applying one of a first voltage and a second voltage to at least one of the plurality of bit lines and applying one of a third voltage and a fourth voltage to at least one of the plurality of virtual ground lines, wherein the voltage applications are based on the determination signal.
A semiconductor memory device, comprising:
A method for accessing data in a memory cell in a semiconductor memory device having a plurality of memory cells divided into a plurality of memory blocks, the method comprising the steps of:
A method for accessing data in a memory cell in a semiconductor memory device having a plurality of memory cells divided into a plurality of memory blocks, the method comprising the steps of:
Dependencies are inferred from the claim text.