Semiconductor memory devices

A semiconductor memory device comprising:

• a plurality of memory cells, each consisting of a capacitor and a transistor;
• a plurality of word lines for individually controlling the transistors of said memory cells;
• plural pairs of bit lines onto which information accumulated in the capacitors of said memory cells is read individually;
• a plurality of sense amplifiers for individually amplifying the information read onto the pairs of bit lines;
• a plurality of pull-down transistors which are equal in number to said word lines, said pull-down transistors connecting, if the corresponding word lines are not selected, the corresponding word lines to the ground;
• and
• precharge circuits for precharging, during standby during which no word line is selected, said pairs of bit lines to a specified potential, said semiconductor memory device further comprising
• a current limiting means for reducing, during standby, a current flowing from each of the word lines to the ground via the pull-down transistor.