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AssigneeTexas Instruments Incorporated
InventorMasashi Hashimoto
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In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.
In a dynamic random access memory having a plurality of storage cells, wherein each storage cell is coupled to one bitline of a bitline pair, a method for reducing the time required to measure the data retention time parameter in a dynamic random access memory unit storage cell, the method comprising the steps of:
A storage cell in a dynamic random access memory, said storage cell comprising:
Apparatus for testing a storage cell comprising:
Dependencies are inferred from the claim text.