Semiconductor memory device and defective memory cell correction circuit

A semiconductor memory device comprising:

• a plurality of arrays of memory cells;
• each of said arrays of memory cells being arranged in a matrix of rows and columns of individual memory cells;
• multiple redundant memory cells for replacement of defective memory cells included in said matrix of rows and columns of individual memory cells for each array of memory cells;
• address generating means for providing a memory address signal to selectively drive one of the row and column of memory cells included in an array of memory cells;
• multiple programmable fuses having respective input means, each of the input means of said programmable fuses being connected to said address generating means for receiving the memory address signal, said input means for a first one of said programmable fuses coupling one end of said first fuse to a first voltage, said input means for a second one of said programmable fuses coupling one end of said second fuse to a second voltage which is the complement of said first voltage;
• an electrical connection node common to each of said fuses each of said fuses having a second end as an output connected to said common node;
• address coincidence signal generating means connected to said common node and generating an address coincidence signal in response to outputs received and indicative of a specific defective memory cell;
• and
• means connected to said address coincidence signal generating means for accessing said multiple redundant memory cells and replacing said specific defective memory cell of a memory cell array with a redundant memory cell from said multiple redundant memory cells in response to receiving the address coincidence signal from said address coincidence signal generating means.