Column repair circuit for integrated circuits

A column repair circuit for use in a semiconductor memory including a matrix of regular memory cells and a spare memory cell, comprising:

• a plurality of bit lines and bit bar lines;
• a plurality of data bus lines and data bus bar lines;
• input/output selecting means for:
• selecting one of the data bus lines and one of the data bus bar lines corresponding to a faulty regular memory cell in response to an input control signal;
• connecting the selected data bus line and the selected data bus bar line to a spare bit line and a spare bit bar line connected to the spare memory cell;
• developing an output signal on a control line corresponding to the selected data bus line and the selected data bus bar line, the output signal having a predetermined level;
• and
• developing additional output signals on additional control lines, each said additional control lines corresponding to one of the non-selected data bus lines and non-selected data bus bar lines, the additional output signals having a level different than the predetermined level;
• wherein said input/output switching means further comprises a plurality of fuse elements, each connected between an input line to which the input control signal is applied and one of a plurality of nodes to which the output signals are applied, all of said plurality of fuse elements, except for the one fuse element corresponding to the selected data bus and line and data bus bar line, being cut to thereby disconnect the input control signal from the remaining non-selected data bus and data bus bar lines;
• decoding means for decoding address signals and the output signals provided by the input/output selecting means;
• and
• switching means for connecting and disconnecting the bit lines and the bit bar lines to and from the data bus lines and the data bus bar lines respectively in response to decoder output signals from the decoding means.