Low voltage one transistor flash EEPROM cell using Fowler-Nordheim programming and erase
AssigneeRohm Co., Ltd.
InventorsShang-De Chang, Jia-Hwang Chang, Edwin Chow
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Abstract
A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.
Claims28
An electrically erasable and programmable memory device having a plurality of storage sites, a plurality of row address lines, a plurality of column address lines, and a plurality of source lines, wherein each combination of one of the plurality of row address lines and one of the plurality of column address lines define a different one of the plurality of storage sites, and further wherein each of the plurality of storage sites comprises a single transistor formed on a substrate which is a selected potential and including:
- a source coupled to an associated one of the plurality of source lines;
- a drain coupled to an associated one of the plurality of column address lines;
- a control gate coupled to an associated one of the plurality of row address lines;
- and
- a floating gate positioned between the gate and the source and drain;
- and further including
- first means for inducing Fowler-Nordheim tunneling of electrons from the source to the floating gate when the associated row address line is elevated to a first predetermined potential above that of the associated one of the source lines;
- and
- second means for inducing Fowler-Nordheim tunneling of electrons from the floating gate to the drain when a predetermined negative potential which is below the selected potential of the substrate is supplied to the associated row address line.
A method of setting the logical condition of a cell in an electrically erasable and programmable memory device of the type having a plurality of cells each comprising a single transistor having a source, a drain, a control gate, and a floating gate positioned between the control gate and the source and drain and each having a voltage threshold, the method comprising the steps of:
- (a) inducing Fowler-Nordheim tunneling of electrons from the source to the floating gate of each cell to raise the voltage threshold to a first level;
- and
- (b) inducing Fowler-Nordheim tunneling of electrons from the floating gate to the drain of selected cells to lower the voltage threshold to a second level.
Dependencies are inferred from the claim text.