Device for calculating parity bits associated with a sum of two numbers

An adder for adding two binary numbers (A,B), said adder comprising:

• means for generating a carry word (C) and producing a result (S), using K groups, with K.gtoreq.2, of m consecutive bits extracted from said binary numbers (A,B), carry word (C) and result (S) and formed respectively by bits a.sub.i,j, b.sub.i,j, c.sub.i,j and s.sub.i, j, where i={1,2, . . . , K} and indicates one of said K groups and i=1 for the m least significant bits, j={1,2, . . . , m} and indicates a significance of a bit in a group, c.sub.1,1, is a first input carry bit for the adder and c.sub.i,1, with i={2, . . . , K}, are second input carry bits, said generating means calculating, for i.noteq.1 and j={1,2, . . . , m}, the following values:
• p.sub.i,j =a.sub.i,j .sym.b.sub.i,j
• g.sub.i,j =a.sub.i,j .multidot.b.sub.i,j
• and, for i=1, the following values:
• p.sub.1,j =a.sub.1,j .sym.b.sub.1,j
• for
• j={2, . . . , m}
• g.sub.1,1 =a.sub.1,1 .multidot.b.sub.1,1 +a.sub.1,1 .multidot.c.sub.1,1 +b.sub.1,1 .multidot.c.sub.1,1
• g.sub.1,j =a.sub.1,j .multidot.b.sub.1,j
• for
• j={2, . . . , m};
• a parity generator circuit (50', 60) receiving said calculated values and K parity bits of said respective binary numbers (A,B) and calculating K parity bits (PS.sub.i) of said respective K groups extracted from said result (S), said parity generator circuit including a first operator (61a) for calculating a value G.sub.1,j of G.sub.i,j, with i=1, as follows:
• G.sub.1,j =g.sub.1,j +p.sub.1,j .multidot.G.sub.1,j-1
• for
• j={2, . . . , m}
• and with G.sub.1,1 =g.sub.1,1
• and a second operator (61b) for calculating:
• Y.sub.1 =c.sub.1,1 .sym.G.sub.1,1 .sym.G.sub.1,2 .sym. . . . .sym.G.sub.1,j . . . .sym.G.sub.1,m-1 .sym.PA.sub.1 .sym.PB.sub.1
• where PA.sub.1 and PB.sub.1 are values of said parity bits PA.sub.i and PB.sub.i, with i=1 and Y.sub.1 is a value corresponding to a parity bit PS.sub.1 of said parity bits PS.sub.i with i=1.