US 5,689,450 AGranted

Parallel processor

AssigneeSony Corporation

InventorsMasuyoshi Kurokawa, Takao Yamazaki

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Abstract

A parallel processor for processing a plurality of pieces of data includes a number of unitary processing units provided in parallel equal to the number of pieces of data. Each of the unitary processing units includes a memory circuit connected to a processing element which exchanges data with two adjoining unitary processing units. Each of the processing elements includes a full adder, a logical operation circuit for performing a logical operation on two inputs connected to a first input of the full adder and a plurality of selector circuits. A first selector circuit selects first data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A second selector circuit selects second data from memory circuits of the unitary processing unit and an adjoining unitary processing unit. A third selector circuit selects the second data selected by the second selector circuit as a first input to the logical operation circuit. A fourth selector circuit selects the first data selected by the first selector circuit as a second input to the logical operation circuit. A fifth selector circuit selects the second data selected by the second selector circuit as a second input to the full adder. A sixth selector circuit selects the carrier output of the full adder as a third input to the full adder.

A parallel processor for processing of an input signal comprised of a plurality of pieces of data per period, comprising:

a plurality of unitary processing units provided in parallel in a number corresponding to the plurality of pieces of data and performing processing for each piece of data;
each of said unitary processing units being comprised so as to enable the exchange of data with two adjoining unitary processing units, each of said unitary processing units comprised of a memory circuit and a processor element connected to said memory circuit;
each of said processor elements including:
a full adder;
a logical operation circuit for performing a logical operation on two inputs connected to a first input of said full adder;
a first selector circuit for selecting one of a first data from said memory circuit in said unitary processing unit and a first data from an adjoining memory circuit in an adjoining unitary processing unit;
a second selector circuit for selecting on of a second data from said memory circuit in said unitary processing unit and a second data from another adjoining memory circuit in another adjoining unitary processing unit;
a third selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a first input for said logical operation circuit;
a fourth selector circuit for selecting one of the first data selected by the first selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for said logical operation circuit;
a fifth selector circuit for selecting one of the second data selected by the second selector circuit, the logical value 1, and the logical value 0 and outputting the same as a second input for said full adder;
a sixth selector circuit or selecting one of a carrier output of said full adder, the logical value 1, and the logical value 0 and outputting the same as a third input for said full adder.

8 more elements

Abstract

Claims8