Decimation filter
OwnerTapio Saramaki, Tapani Ritoniemi +4inventors
InventorsTapio Saramaki, Tapani Ritoniemi, Ville Eerola, Timo Husu, Eero Pajarre, Seppo Ingalsuo
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Abstract
The invention relates to a decimation filter comprising a direct cascade arrangement of digital first order and second order integration and derivation stages (22, 23, 25, 27) and a decimation stage. The decimation filter structure of the invention comprises additional branches (28, 29, 30, 31) for shifting the location of the attenuation zeros of the decimation filter and thereby reducing the order M and the number of structural elements M of the required filter.
Claims12
A decimation filer comprising a cascade arrangement of the following elements in the given order:
- M.sub.1 digital first order integration stages having a clock rate F.sub.s and a delay of one clock cycle,
- M.sub.2 digital second order integration stages having a clock rate F.sub.2 and a delay of two clock cycles,
- a decimation stage for decreasing the sampling frequency of the output signal from the last integration stage by a predetermined decimation ration K,
- M digital derivation stages having a clock rate F.sub.s /K, each comprising a delay element stage for delaying the input signal for one clock cycle and a subtractor element stage for subtracting the input signal from the output signal of the delay element, wherein M=M.sub.1 +2M.sub.2,
- M.sub.2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to the M.sub.1 -stage integrator and the output of the derivation stage of the i:th second stage subsequent to the decimation block in the main branch a signal processing branch is connected including, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F.sub.s of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F.sub.s /K, and a scaling element having a scaling factor .alpha..sub.i where i=1,2,3, . . . , M.sub.2.
A decimation filter comprising a cascade arrangement of the following elements in the given order:
- M.sub.1 digital first order integration stages having a clock rate F.sub.s and a delay of one clock cycle,
- M.sub.2 digital second order integration stages having a clock rate F.sub.2 and a delay of two clock cycles,
- a decimation stage for decreasing the sampling frequency of the output signal from the last integration stage by a predetermined decimation ratio K,
- M digital derivation stages having a clock rate F.sub.s /K, each comprising a delay element stage for delaying the input signal for one clock cycle and a subtractor element stage for subtracting the input signal from the output signal of the delay element, wherein M=M.sub.1 +2M.sub.2,
- M.sub.2 signal processing branches in such a way that between the input of the i:th second stage integrator subsequent to M.sub.1 and the output of the main branch a signal processing branch is connected including, in series configuration, a first delay element having a delay of i clock cycles at sampling frequency F.sub.s of the output signal, a decimation stage for decreasing the sampling frequency of the first delay element by a predetermined decimation ratio K, a second delay element having a delay of i clock cycles at sampling frequency F.sub.s /K, a (M.sub.1 +2(M.sub.2 -i))-stage derivation block, and a scaling element having a scaling factor .alpha..sub.1, where i=1,2,3, . . . , M.sub.2.
Dependencies are inferred from the claim text.