Buffer management in an image formatter

An image formatter for processing encoded video data comprising:

• an input element for receiving encoded data representing video frames, said data arriving as a sequence of tokens at an encoded frame rate for output or display at a display frame rate;
• a memory defining at least three buffers for storage of the encoded data, wherein said received data is initially stored in a first said buffer;
• a write address generator for generating addresses for data being stored in said first buffer;
• a read address generator for generating addresses for reading data stored in said first buffer;
• a presentation number counter;
• an output interface linked to said read address generator that produces output data at said display frame rate;
• and
• a buffer manager responsive to control information in said tokens, to said encoded frame rate, and to said display frame rate, said buffer manager dynamically allocating and deallocating said at least three buffers as arrival buffers for reference by said write address generator, and as display buffers for reference by said read address generator, said buffer manager clearing said buffers for occupation by subsequently arriving data, and maintaining status information of said buffers, wherein said status information comprises a state VACANT, wherein a said buffer is available, a state IN USE, wherein a said buffer can be referenced by said write address generator, a state FULL, wherein a said buffer is occupied by data, and a state READY wherein a said buffer is reallocated as a display buffer;
• wherein responsive to said presentation number counter and a current picture number contained in the encoded data said buffer manager asserts a late arrival signal indicating that a buffer in said state READY is not in synchronization with said display frame rate;
• a state machine for controlling said buffer manager, said state machine transitioning among a plurality of states, including:
• a first transition from a first state PRES0, to a second state PRES1, wherein said status information of said buffers are evaluated;
• a second transition from said state PRES1 to a third state DRQ wherein a pending request for said display buffer is evaluated;
• and
• a third transition from said stage DRQ to a fourth state TOKEN, wherein tokens of received data are examined;
• whereby a status of said arrival buffer can be updated;
• and
• a plurality of 2-wire Interfaces each comprising:
• a sender a receiver, and a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready, wherein said buffer manager communicates with said read address generator, and with said write address generator via said 2-wire interfaces.