Vertical reset genereator circuit
AssigneesSony Corporation, Sony Electronics Inc.
InventorsMehrdad Nayebi, Duc Ngo
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AssigneesSony Corporation, Sony Electronics Inc.
InventorsMehrdad Nayebi, Duc Ngo
Estimating the term…
A vertical reset generator monitors a composite video signal and generates a vertical reset pulse which is active during the presence of serration pulses within the composite video signal. The synchronization pulses within the input composite video signal are separated by a sync separator circuit. The output of the sync separator circuit, including horizontal sync pulses, equalizing pulses and serration pulses, is provided to a charging circuit which charges up a capacitor when the output of the sync separator circuit is at a low level and discharges the capacitor when the output of the sync separator circuit is at a high level. The serration pulses are at a low level for a greater time period than the equalizing pulses. The charge built up across the capacitor is therefore greater during a serration pulse than during an equalizing pulse. An up threshold level is set so that the voltage built up across the capacitor will not reach the threshold during the low level of an equalization pulse but will reach it during the low level of a serration pulse. During the first serration pulse, the charge across the capacitor rises above the up threshold level causing the vertical reset generator to activate a vertical reset pulse. A down threshold level is set so that the voltage across the capacitor will not fall below that level during the high level of a serration pulse but will fall below it during the next equalizing pulse. During the first equalizing pulse after a serration pulse, the charge across the capacitor falls below the down threshold level causing the vertical reset generator to deactivate the vertical reset pulse. The vertical reset pulse remains inactive until the next serration pulse.
A vertical reset generator circuit for generating a vertical reset signal representing a vertical reset time period within a video system, the circuit comprising:
A method of generating a vertical reset pulse within a video system comprising the steps of:
A method of generating a vertical reset pulse representative of the presence of serration pulses within a composite video signal, comprising the steps of:
A vertical reset generator circuit for generating a vertical reset signal representing a vertical reset time period within a video system, the circuit comprising:
Dependencies are inferred from the claim text.