Multiple current digital-analog converter capable of reducing output glitch

A multiple current digital-analog converter for converting a digital input signal having a plurality of bits to a corresponding analog value current for output, comprising:

• a plurality of unit current source cells;
• and
• current summing means for summing output currents from said unit current source cells;
• wherein each of said unit current source cells includes:
• signal output and holding means for receiving each corresponding bit signal of said digital input signal before an arrival of a first external timing signal and for outputting the corresponding bit signal and an inverted bit signal acquired by inverting said corresponding bit signal after the arrival of said first external timing signal while simultaneously holding the corresponding bit signal and the inverted bit signal;
• a differential switch circuit including a first switch and a second switch;
• a constant current source for outputting a constant current to said current summing means via said differential switch circuit;
• and
• a first driving circuit and a second driving circuit each controlled by said corresponding bit signal and the inverted bit signal respectively in order to open and close said first switch and said second switch of said differential switch circuit in a complementary manner so that a delay time for the switch closing operation will be longer than delay time for the switch opening operation.

A multiple current digital-analog converter for converting a digital input signal having a plurality of bits to a corresponding analog value current for output, comprising:

• a plurality of unit current source cells;
• and
• current summing means for summing output currents from said unit current source cells;
• wherein each of said unit current source cells includes:
• signal output and holding means for receiving each bit signal of said digital input signal before an arrival of a first external timing signal and for outputting the corresponding bit signal and an inverted bit signal acquired by inverting said corresponding bit signal after the arrival of said first external timing signal while simultaneously holding the corresponding bit signal and the inverted bit signal;
• signal output and holding means for receiving each
• a differential switch circuit including a first switch and a second switch;
• a constant current source for outputting a constant current to said current summing means via said differential switch circuit;
• a first driving circuit and a second driving circuit controlled by said corresponding bit signal and the inverted bit signal respectively in order to open and close said first switch and said second switch of said differential switch circuit in a complementary manner;
• and
• driving circuit control means including two transmission routes with different delay time from each other for transmitting said corresponding bit signal and said inverted bit signal to said first driving circuit and said second driving circuit respectively, said driving circuit control means switching relative to said first driving circuit and said second driving circuit said two transmission routes in a complementary manner in response to a second external timing signal.