Post-fabrication programmable integrated circuit ring oscillator

A DRAM integrated circuit comprising:

• a memory cell array adapted to store binary information;
• an addressing circuit operatively connected to said memory cell array for selectively providing access to memory cells in said memory said array for writing data into and reading data from said memory cell array;
• a data buffer circuit operatively connected to said memory cell array for routing data to and from said memory cell array for respectively writing data into and reading data from said memory cell array;
• a charge pump operatively connected to said memory cell array for providing a voltage for use by said memory cell array, said charge pump altering the magnitude of said voltage toward a target voltage in response to a clock signal;
• and
• a programmable ring oscillator generating said clock signal, said oscillator including 2N-1 inverting circuits where N is an integer equal to or greater than 2, said inverting circuits being connected in series with each other with said clock signal being generated at an output of one of said inverting circuits, said oscillator further including a plurality of programmable connections extending from an output of one of said inverting circuits to an input of a respective other of said inverting circuits located an odd number of inverting circuits away from the output of said one inverting circuit, said programmable connections being programmable after fabrication of said integrated circuit to short circuit a selected programmable connection and open circuit all but said selected programmable connection thereby placing 2M-1 of said inverting circuits in a loop where M is an integer between 1 and N, whereby the frequency of said clock signal may be adjusted after fabrication of said integrated circuit by programming said programmable connections.

A DRAM integrated circuit comprising:

• a memory cell array adapted to store binary information;
• an addressing circuit operatively connected to said memory cell array for selectively providing access to memory cells in said memory cell array for writing data into and reading data from said memory cell array;
• a data buffer circuit operatively connected to said memory cell array for routing data to and from said memory cell array for respectively writing data into and reading data from said memory cell array;
• a refresh circuit refreshing data stored in at least part of said memory cell array responsive to a refresh signal;
• and
• a programmable ring oscillator periodically generating said refresh signal, said oscillator including 2N-1 inverting circuits where N is an integer equal to or greater than 2, said inverting circuits being connected in series with each other with said refresh signal being generated at an output of one of said inverting circuits, said oscillator further including a plurality of programmable connections extending from an output of one of said inverting circuits to an input of a respective other of said inverting circuits located an odd number of inverting circuits away from the output of said one inverting circuit, said programmable connections being programmable after fabrication of said integrated circuit to short circuit a selected programmable connection and open circuit all but said selected programmable connection thereby placing 2M-1 of said inverting circuits in a loop where M is an integer between 1 and N, whereby the frequency of said refresh signal may be adjusted after fabrication of said integrated circuit by programming said programmable connections.

A computer system, comprising:

• a data processor circuit having an address bus, a data bus, and a control bus;
• an input/output device operatively connected to said data processor circuit for allowing data to be input to or output from said computer system;
• and
• a DRAM integrated circuit having an address bus connected to the address bus of said data processor circuit, a data bus connected to the data bus of said data processor circuit, and control lines connected at least a portion of the control bus of said data processor circuit, said DRAM integrated circuit comprising:
• a memory cell array adapted to store binary information;
• an addressing circuit operatively connected to the address bus of said DRAM integrated circuit and to said memory cell array for selectively providing access to memory cells in said memory cell array for writing data into and reading data from said memory cell array;
• a data buffer circuit operatively connected to the data bus of said DRAM integrated circuit and to said memory cell array for routing data to and from said memory cell array for respectively writing data into and reading data from said memory cell array;
• and
• a programmable ring oscillator generating an oscillator signal for use by said DRAM integrated circuit, said oscillator including 2N-1 inverting circuits where N is an integer equal to or greater than 2, said inverting circuits being connected in series with each other with said clock signal being generated at an output of one of said inverting circuits, said oscillator further including a plurality of programmable connections extending from an output of one of said inverting circuits to an input of a respective other of said inverting circuits located an odd number of inverting circuits away from the output of said one inverting circuit, said programmable connections being programmable after fabrication of said integrated circuit to short circuit a selected programmable connection and open circuit all but said selected programmable connection thereby placing 2M-1 of said inverting circuits in a loop where M is an integer between 1 and N, whereby the frequency of said oscillator signal may be adjusted after fabrication of said integrated circuit by programming said programmable connections.