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US 5,689,208 AGranted
Charge pump circuit for high side switch
AssigneeInternational Rectifier Corporation
InventorBruno C. Nadd
Life of this patent
Estimating the term…
Abstract
A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V.sub.CC terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.
Claims11
A charge pump circuit for a gate controlled MOS power semiconductor device;
- said gate controlled MOS power semiconductor device having a V.sub.CC input voltage terminal, a ground terminal and a control terminal;
- said charge pump circuit comprising, in combination:
- a square wave oscillator having an output terminal;
- an inverter buffer connected to said oscillator output terminal;
- a charge storage capacitor coupled to the output of said inverter buffer;
- a first coupling circuit for coupling said capacitor to said control terminal of said gate controlled MOS power semiconductor device;
- a second coupling circuit for coupling said V.sub.CC input voltage terminal to the node between said capacitor and said first coupling circuit whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V.sub.CC terminal and through said second coupling circuit and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V.sub.CC terminal are applied in series through said first coupling circuit to said control terminal of said gate controlled MOS power semiconductor device;
- and wherein said first coupling circuit comprises a depletion mode MOSFET having source and drain terminals connected to said capacitor and said control terminal of said gate controlled MOS power semiconductor device respectively and having its substrate connected to the output of said inverter buffer, a resistive circuit connected from said capacitor to the gate of said depletion mode MOSFET, and a first control MOSFET connected between said gate of said depletion mode MOSFET and said ground terminal and having a gate connected to said oscillator output terminal.
5 more elements
A charge pump circuit for a gate controlled MOS power semiconductor device;
- said gate controlled MOS power semiconductor device having a V.sub.CC input voltage terminal, a ground terminal and a control terminal;
- said charge pump circuit comprising, in combination:
- a square wave oscillator having an output terminal;
- an inverter buffer connected to said oscillator output terminal;
- a first charge storage capacitor coupled to the output of said inverter buffer;
- a first coupling circuit for coupling said first capacitor to said control terminal of said gate controlled MOS power semiconductor device;
- a second coupling circuit for coupling said V.sub.CC input voltage terminal to the node between said first capacitor and said first coupling circuit whereby, when the output of said inverter buffer is low, said first capacitor is charged from the voltage at said V.sub.CC terminal and through said second coupling circuit and, when said output of said inverter buffer is high, the voltage of said first capacitor plus the voltage of said V.sub.CC terminal are applied in series through said first coupling circuit to said control terminal of said gate controlled MOS power semiconductor device;
- and wherein said second coupling circuit includes a second charge storage capacitor connected between said V.sub.CC input voltage terminal and said oscillator output terminal and a first control MOSFET connected between said V.sub.CC input voltage terminal and said first coupling circuit and having a gate coupled to the output of said inverter buffer and to said second capacitor such that when the output of said inverter buffer is low, said second capacitor boosts the voltage supplied to the gate of said control MOSFET, thereby turning said control MOSFET on and allowing said first capacitor to charge, and when said output of said inverter buffer is high, said first control MOSFET is off, thereby permitting the charge on said first capacitor to transfer to said control terminal of said gate controlled MOS semiconductor device.
5 more elements
A charge pump circuit for a gate controlled MOS power semiconductor device;
- said gate controlled MOS power semiconductor device having a V.sub.CC input voltage terminal, a ground terminal and a control terminal;
- said charge pump circuit comprising, in combination:
- a square wave oscillator having an output terminal;
- an inverter buffer connected to said oscillator output terminal;
- a charge storage capacitor coupled to the output of said inverter buffer;
- a first coupling circuit coupling said capacitor to said control terminal of said gate controlled MOS power semiconductor device;
- a second coupling circuit for coupling said V.sub.CC input voltage terminal to the node between said capacitor and said first coupling circuit whereby, when the output of said inverter buffer is low, said capacitor is charged from the voltage at said V.sub.CC terminal and through said second coupling circuit and, when said output of said inverter buffer is high, the voltage of said capacitor plus the voltage of said V.sub.CC terminal are applied in series through said first coupling circuit to said control terminal of said gate controlled MOS power semiconductor device;
- wherein said second coupling circuit includes a first control MOSFET connected between said V.sub.CC input voltage terminal and said first coupling circuit, a second control MOSFET coupled between the gate of said first control MOSFET and said ground terminal and having a gate connected to said the output of said inverter buffer, a diode and a second charge storage capacitor connected in series between said V.sub.CC input voltage terminal and said oscillator output terminal, and a resistor connected between the gate of said first control MOSFET and a node located between the cathode of said diode and said second charge storage capacitor.
5 more elements
Dependencies are inferred from the claim text.