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US 5,689,200 AGranted
High speed glitch-free transition detection circuit with disable control
AssigneeEtron Technology, Inc.
InventorsTah-Kang Joseph Ting, Jeng-Tzong Shih, Yung-Ching Hsieh
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Abstract
A high speed clock-positive edge detection circuit with chip select control that produces a glitch-free transition detection pulse is described. The circuit comprises Logic, Conditioning and Output Sections. An n-channel transistor is connected between output C, output B and the Chip Select input. This eliminates glitches that would otherwise be present, as in the prior art.
Claims17
An edge detection circuit comprising:
- a logic section having a first and a second signal input and a first output of the logic section and a second output of the logic section, said logic section outputs providing signal gating;
- a conditioning section coupled to said first and second signal inputs and a third input, said third input connected to said first output of said logic section, and an output, said output of said conditioning section connected to a terminal C, said conditioning section determining the voltage level at said terminal C;
- an output section with an input and an output, said input of said output section connected to said terminal C, said output of said output section providing a disable control;
- and an N-channel transistor section having a source terminal, a drain terminal and a gate terminal, said drain terminal connected to said terminal C, said source terminal connected to said second output of the login section, and said gate terminal connected to the second signal input, said N-channel transistor section inhibiting a glitch from propagating through to said terminal C.
1 more element
An edge detection circuit comprising:
- a logic section having a first and a second signal input and a first output of the logic section and a second output of the logic section, said logic section outputs providing signal gating;
- a conditioning section coupled to said first and second signal inputs and a third input, said third input connected to said first output of said logic section, and an output, said output of said conditioning section connected to a terminal C, said conditioning section determining the voltage level at said terminal C;
- an output section with an input and an output, said input of said output section connected to said terminal C, said output of said output section providing a disable control;
- and an N-channel transistor section having a source terminal, a drain terminal and a gate terminal, said drain terminal connected to said terminal C, said source terminal connected to said second output of the logic section, and said gate terminal connected to the second signal input, said N-channel transistor section inhibiting a glitch from propagating through to said terminal C, said N-channel transistor section comprising a blocking n-channel transistor which is biased outside the saturation region for a fast turn-off.
1 more element
Dependencies are inferred from the claim text.